Dynamic vector lane broadcasting
View Patent ↗An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes first partition and a second partition. The second partition includes video pre-processing circuitry that identifies regions of a video frame to be presented on a screen or monitor that don't change or regions that can have one or more of resolution and color accuracy be below a threshold. The first partition includes a parallel data processor with one or more compute units, each with multiple lanes of execution. Based on the identified regions, the first partition generates an execution mask indicating which lanes of the compute units are inactive. The parallel data processor copies result data from the active lanes to outputs of the inactive lanes.
1 . A processor comprising:
at least one compute unit comprising:
a plurality of lanes, each configured to perform processing associated with a task; and
circuitry configured to:
receive data that includes a first indication of first portions of the task that are to be processed and second portions of the task that are to be skipped;
perform processing using at least one lane identified as active, wherein the first indication is usable to control whether individual lanes of the plurality of lanes are to be active or inactive and cause a fetch of data for active lanes while skipping fetch of data for inactive lanes; and
provide a result from the at least one lane identified as active to at least one inactive lane, wherein the inactive lane receives the result without the second portions of the task having been processed by any of the plurality of lanes.
2 . The processor as recited in claim 1 , wherein the circuitry is further configured to perform power gating for the one or more lanes of the plurality of lanes, based at least in part on the data that includes the first indication.
3 . The processor as recited in claim 1 , wherein the first indication has been generated based at least in part on one or more characteristics of source data of the task.
4 . The processor as recited in claim 1 , wherein the circuitry is further configured to generate the data that includes the first indication as a ratio indicating a number of active lanes to a number of total lanes of the plurality of lanes.
5 . The processor as recited in claim 1 , wherein the circuitry is further configured to:
receive an indication of a power domain from a power controller, wherein the power domain comprises one or more of an operating power supply voltage for the processor and an operating clock frequency for the processor; and
generate the data that includes the first indication, based at least in part on the indication of the power domain.
6 . The processor as recited in claim 1 , wherein the circuitry is further configured to generate the data that includes the first indication based on data items corresponding to pixels of a region of a frame with a resolution or color accuracy below a threshold.
7 . The processor as recited in claim 6 , wherein the circuitry is further configured to generate data that includes a second indication of which portions of the task are to be processed and which portions are to be skipped, wherein the second indication is based at least in part on the first indication.
8 . A method, comprising:
processing tasks, by a parallel data processor comprising at least one compute unit with a plurality of lanes comprising circuitry configured to process a task comprising a plurality of threads;
generating, by the parallel data processor, data that includes a first indication of first portions of the task that are to be processed and second portions of the task that are to be skipped;
processing, by the parallel data processor, the task using at least one lane identified as active, wherein the first indication is usable to control whether individual lanes of the plurality of lanes are to be active or inactive and cause a fetch of data for active lanes while skipping fetch of data for inactive lanes; and
providing, by the parallel data processor, a result from the at least one lane identified as active to at least one inactive lane, wherein the inactive lane receives the result without the second portions of the task having been processed by any of the plurality of lanes.
9 . The method as recited in claim 8 , further comprising performing, by the parallel data processor, power gating for the one or more lanes of the plurality of lanes, based at least in part on the data that includes the first indication.
10 . The method as recited in claim 8 , wherein the first indication has been generated based at least in part on one or more characteristics of source data of the task.
11 . The method as recited in claim 8 , further comprising generating the data that includes the first indication as a ratio indicating a number of active lanes of to a number of total lanes of the plurality of lanes.
12 . The method as recited in claim 8 , further comprising:
receiving, by the parallel data processor, an indication of a power domain from a power controller, wherein the power domain comprises one or more of an operating power supply voltage for the parallel data processor and an operating clock frequency for the parallel data processor; and
generating, by the parallel data processor, the data that includes the first indication based at least in part on the indication of the power domain.
13 . The method as recited in claim 8 , further comprising generating, by the parallel data processor, the data that includes the first indication based on data items of the plurality of threads corresponding to pixels of a region of a frame with a resolution or color accuracy below a threshold.
14 . The method as recited in claim 13 , further comprising generating, by the parallel data processor, data that includes a second indication of which portions of the task are to be processed and which portions are to be skipped, wherein the second indication is based at least in part on the first indication.
15 . A computing system comprising:
a memory configured to store data to be processed during execution of a task;
a parallel data processor comprising:
at least one compute unit with a plurality of lanes comprising circuitry configured to process the task comprising a plurality of threads;
a code generator configured to generate data that includes a first indication of first portions of the task that are to be processed and second portions of the task that are to be skipped; and
circuitry configured to:
receive the data that includes the first indication;
process the task using at least one lane identified as active, wherein the first indication is usable to control whether individual lanes of the plurality of lanes are to be active or inactive and cause a fetch of data for active lanes while skipping fetch of data for inactive lanes; and
provide a result from the at least one lane identified as active to at least one inactive lane, wherein the inactive lane receives the result without the second portions of the task having been processed by any of the plurality of lanes.
16 . The computing system as recited in claim 15 , wherein the circuitry is further configured to perform power gating for the one or more lanes of the plurality of lanes, based at least in part on the data that includes the first indication.
17 . The computing system as recited in claim 15 , wherein the first indication has been generated based at least in part on one or more characteristics of source data of the task.
18 . The computing system as recited in claim 15 , wherein the circuitry is further configured to generate the data that includes the first indication as a ratio indicating a number of active lanes of to a number of total lanes of the plurality of lanes.
19 . The computing system as recited in claim 15 , further comprising a power controller, wherein the code generator is further configured to:
receive an indication of a power domain from the power controller, wherein the power domain comprises one or more of an operating power supply voltage for the parallel data processor and an operating clock frequency for parallel data the processor; and
generate the data that includes the first indication based at least in part on the indication of the power domain.
20 . The computing system as recited in claim 15 , wherein the code generator is further configured to generate the data that includes the first indication based on data items of the plurality of threads corresponding to pixels of a region of a frame with a resolution or color accuracy below a threshold.