IP Library › Granted Patent US 12,547,510
Granted Patent B2
US 12,547,510 · App. 18/762,642 · Granted Feb 10, 2026

Memory system and data processing system including the same

Inventors: Eung-Bo Shim (Gyeonggi-do, KR); Hyung-Sup Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F11/2094G06F11/073G06F11/076G06F11/1658G06F11/20G06F11/3037G06F11/326G11C29/08G11C29/42G11C29/4401G11C29/52G11C29/765G11C29/81G11C29/832G06F2201/82G11C2029/4402
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Quick Facts
Patent No.
US 12,547,510
App. No.
18/762,642
Granted
Feb 10, 2026
Kind
B2
Abstract

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

Claims (8)

1 . A data processing system comprising:

a compute system; and

a memory system, coupled to the compute system via an interconnect device, the memory system comprising a plurality of groups of memory devices and a plurality of controllers, wherein each group of memory devices includes a serial presence detect (SPD) component and each of the controllers is coupled to a corresponding group of memory devices for memory training,

wherein each of the controllers acquires characteristic data from the SPD components in the corresponding group of memory devices when power is supplied, providing the acquired characteristic data to the compute system.

2 . The data processing system of claim 1 , wherein each of the controllers performs the memory training for the corresponding group of memory devices based on the acquired characteristic data; and

wherein the compute system performs interface training with the controllers, and performs input and output testing for the plurality of groups of memory devices.

3 . The data processing system of claim 2 , wherein each of the controllers includes a nonvolatile memory device, and stores the acquired characteristic data and a result data of the memory training in the nonvolatile memory device.

4 . The data processing system of claim 3 , wherein each of the controllers acquires the result data of the memory training of a memory device from the nonvolatile memory device, when power is supplied and characteristic data of the memory device coincides with the characteristic data stored in the nonvolatile memory device.

Priority Claims (4)
KR 10-2017-0143428 · Oct 31, 2017 · national
KR 10-2017-0148004 · Nov 8, 2017 · national
KR 10-2018-0004390 · Jan 12, 2018 · national
KR 10-2019-0005161 · Jan 15, 2019 · national
Continuity (7)
Division 17949287 · Sep 21, 2022
Division 16851660 · Apr 17, 2020
Continuation In Part 16674935 · Nov 5, 2019
Continuation In Part 16189984 · Nov 13, 2018
Continuation In Part 16041258 · Jul 20, 2018
Continuation In Part 16039220 · Jul 18, 2018
Related Publication 20240354210A1 · Oct 24, 2024
References Cited (9)
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