Erase pulse loop dependent adjustment of select gate erase bias voltage
Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.
1 . A memory device comprising:
an array of memory cells; and
control logic, operatively coupled with the array of memory cells, to perform operations comprising:
initiating an erase operation including a set of erase loops to erase one or more memory cells of the array of memory cells;
during a first erase loop of the set of erase loops:
causing a first erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells of the memory device;
causing a first erase bias voltage having an initial voltage level to be applied to a first select gate adjacent to the source line, wherein the first erase bias voltage is based on a first delta voltage level; and
causing a second erase bias voltage having the initial voltage level to be applied to a second select gate associated with the source line, wherein the second select gate is adjacent to the first select gate; and
during a subset of erase loops following the first erase loop:
causing a second erase pulse having the erase voltage level to be applied to the source line;
causing a first adjusted erase bias voltage to be applied to the first select gate; and
causing a second adjusted erase bias voltage to be applied to the second select gate, wherein the first adjusted erase bias voltage is less than the second adjusted erase bias voltage.
2 . The memory device of claim 1 , wherein the initial voltage level equals the erase voltage level minus the first delta voltage level.
3 . The memory device of claim 1 , wherein the first delta voltage level is in a range of approximately OV to approximately 2V.
4 . The memory device of claim 1 , wherein the first adjusted erase bias voltage is based on a first adjusted delta voltage level.
5 . The memory device of claim 4 , wherein the second adjusted erase bias voltage is based on a second adjusted delta voltage level.
6 . The memory device of claim 5 , wherein the first adjusted delta voltage level is in a first range of approximately 10V to approximately 14V, and wherein the second adjusted delta voltage level is in a second range of approximately 3V to approximately 6V.
7 . The memory device of claim 1 , wherein the subset of erase loops comprises a second erase loop through a final erase loop.
8 . A method comprising:
initiating, by a processing device, an erase operation including a set of erase loops to erase one or more memory cells of a memory device;
during a first erase loop of the set of erase loops:
causing a first erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells of the memory device;
causing a first erase bias voltage having an initial voltage level to be applied to a first select gate adjacent to the source line, wherein the first erase bias voltage is based on a first delta voltage level; and
causing a second erase bias voltage having the initial voltage level to be applied to a second select gate associated with the source line, wherein the second select gate is adjacent to the first select gate; and
during a subset of erase loops following the first erase loop:
causing a second erase pulse having the erase voltage level to be applied to the source line;
causing a first adjusted erase bias voltage to be applied to the first select gate; and
causing a second adjusted erase bias voltage to be applied to the second select gate, wherein the first adjusted erase bias voltage is less than the second adjusted erase bias voltage.
9 . The method of claim 8 , wherein the initial voltage level equals the erase voltage level minus the first delta voltage level.
10 . The method of claim 8 , wherein the first delta voltage level is in a range of approximately OV to approximately 2V.
11 . The method of claim 8 , wherein the first adjusted erase bias voltage is based on a first adjusted delta voltage level.
12 . The method of claim 11 , wherein the second adjusted erase bias voltage is based on a second adjusted delta voltage level.
13 . The method of claim 12 , wherein the first adjusted delta voltage level is in a first range of approximately 10V to approximately 14V, and wherein the second adjusted delta voltage level is in a second range of approximately 3V to approximately 6V.
14 . The method of claim 8 , wherein the subset of erase loops comprises a second erase loop through a final erase loop.
15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
initiating an erase operation including a set of erase loops to erase one or more memory cells of a memory device;
during a first erase loop of the set of erase loops:
causing a first erase pulse having an erase voltage level to be applied to a source line associated with the one or more memory cells;
causing a first erase bias voltage having an initial voltage level to be applied to a first select gate adjacent to the source line, wherein the first erase bias voltage is based on a first delta voltage level; and
causing a second erase bias voltage having the initial voltage level to be applied to a second select gate associated with the source line, wherein the second select gate is adjacent to the first select gate; and
during a subset of erase loops following the first erase loop:
causing a second erase pulse having the erase voltage level to be applied to the source line;
causing a first adjusted erase bias voltage to be applied to the first select gate; and
causing a second adjusted erase bias voltage to be applied to the second select gate, wherein the first adjusted erase bias voltage is less than the second adjusted erase bias voltage.
16 . The non-transitory computer-readable storage medium of claim 15 , wherein the initial voltage level equals the erase voltage level minus the first delta voltage level.
17 . The non-transitory computer-readable storage medium of claim 15 , wherein the first delta voltage level is in a range of approximately OV to approximately 2V.
18 . The non-transitory computer-readable storage medium of claim 15 , wherein the first adjusted erase bias voltage is based on a first adjusted delta voltage level.
19 . The non-transitory computer-readable storage medium of claim 18 , wherein the second adjusted erase bias voltage is based on a second adjusted delta voltage level.
20 . The non-transitory computer-readable storage medium of claim 19 , wherein the first adjusted delta voltage level is in a first range of approximately 10V to approximately 14V, and wherein the second adjusted delta voltage level is in a second range of approximately 3V to approximately 6V.