Dynamic erase loop dependent bias voltage
Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.
1. An apparatus comprising:
a monitor circuit configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold;
a bias circuit configured to adjust a voltage applied to one or more buffer word lines of the erase block in response to the erase loop count for the data word lines satisfying the threshold; and
an erase circuit configured to perform one or more subsequent erase loops of the erase operation for the data word lines with the adjusted voltage applied to the one or more buffer word lines.
2. The apparatus of claim 1 , wherein the threshold is selected based on a ratio of an initial erase loop count and a program loop count.
3. The apparatus of claim 2 , wherein the ratio of the initial erase loop count and the program loop count comprises two erase loops to one program loop.
4. The apparatus of claim 3 , wherein the erase loop count satisfies the threshold in response to the erase loop count exceeding two erase loops and the bias circuit is configured to adjust the voltage for the one or more buffer word lines for the one or more subsequent erase loops after the two erase loops.
5. The apparatus of claim 1 , wherein the one or more buffer word lines comprise one or more dummy word lines disposed between the data word lines and one or more select gates.
6. The apparatus of claim 5 , wherein the one or more dummy word lines do not store valid data.
7. The apparatus of claim 5 , wherein the adjusted voltage prevents a threshold voltage downshift for the one or more dummy word lines.
8. The apparatus of claim 5 , wherein the adjusted voltage prevents a threshold voltage downshift for the one or more select gates.
9. The apparatus of claim 1 , wherein the adjusted voltage for the one or more buffer word lines comprises an increased voltage higher than an initial voltage applied to the one or more buffer word lines for previous erase loops of the erase operation prior to the one or more subsequent erase loops.
10. The apparatus of claim 9 , wherein the increased voltage reduces a voltage differential between the one or more buffer word lines and a channel for the data word lines from a voltage differential of the previous erase loops, thereby reducing an erase effect of the one or more subsequent erase loops on the one or more buffer word lines from an erase effect of the previous erase loops.
11. The apparatus of claim 1 , wherein the adjusted voltage for the one or more buffer word lines comprises a decreased voltage lower than an initial voltage applied to the one or more buffer word lines for previous erase loops of the erase operation prior to the one or more subsequent erase loops, thereby reducing an erase effect of the one or more subsequent erase loops on the one or more buffer word lines from an erase effect of the previous erase loops.
12. A system comprising:
a non-volatile memory medium comprising a plurality of erase blocks each comprising a plurality of data word lines and one or more dummy word lines between the data word lines and select gates; and
a controller for the non-volatile memory medium, the controller monitoring an erase loop count for each of the erase blocks and increasing a bias voltage on the one or more dummy word lines of an erase block of the plurality of erase blocks in response to the erase loop count for the erase block exceeding a predefined erase loop threshold.
13. The system of claim 12 , wherein the non-volatile memory medium comprises a one program pulse medium and the predefined erase loop threshold is selected based on a ratio of an initial erase loop count for the plurality of erase blocks to the one program pulse for the non-volatile memory medium.
14. The system of claim 12 , wherein the controller comprises an on-die controller of a same integrated circuit device as the non-volatile memory medium.
15. The system of claim 12 , wherein the controller comprises a device controller for a plurality of integrated circuit devices, one of the integrated circuit devices comprising the non-volatile memory medium.