IP Library › Granted Patent US 12,556,085
Granted Patent B1
US 12,556,085 · App. 18/062,519 · Granted Feb 17, 2026

Power conversion circuit with solid state switches

Inventors: David Lidsky (Oakland, CA); Timothy Alan Phillips (Hope, RI)
Assignee: Empower Semiconductor, Inc.
H02M3/158H02M1/0095H02M3/07H02M1/0058
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,556,085
App. No.
18/062,519
Granted
Feb 17, 2026
Kind
B1
Abstract

A switched-mode power regulator circuit has four solid-state switches connected in series and a capacitor and an inductor that regulate power delivered to a load. The solid-state switches are operated such that a voltage at the load is regulated by repetitively (1) charging the capacitor causing a current to flow in the inductor and (2) discharging the capacitor causing current to flow in the inductor. The power regulator circuit may be configured to operate with zero current switching at frequencies in the range of 100 MHz, enabling it to be fabricated on a unitary silicon die along with the load that it powers.

Claims (35)

1 . A power conversion circuit comprising:

a first switch connected to an input terminal;

a second switch connected between the first switch and an output terminal, wherein the second switch is connected to the first switch at a first node;

a third switch connected between the output terminal and a fourth switch, wherein the third switch is connected to the fourth switch at a second node and the fourth switch is connected to a ground;

an inductor coupled between the output terminal and a load; and

a capacitor having a first terminal and a second terminal, the first terminal directly connected to the first node and the second terminal directly connected to the second node,

the capacitor arranged to be coupled to a power supply through a first transistor and a second transistor such that when the first and second transistors are simultaneously in a conductive state, the first terminal is electrically connected to the power supply and the second terminal is electrically connected to the power supply.

2 . The power conversion circuit of claim 1 , wherein the first, the second, the third and the fourth switches are formed on a single silicon-based die.

3 . The power conversion circuit of claim 1 , further comprising a controller comprising circuitry configured to control energy flowing through the first, the second, the third and the fourth switches.

4 . The power conversion circuit of claim 3 , wherein each of the first, the second, the third and the fourth switches includes a gate terminal coupled to the controller.

5 . An electronic component comprising:

a substrate having a plurality of contacts for forming electrical connectors to a circuit board; and

an integrated circuit device attached to the substrate and including:

a first switch connected to an input terminal,

a second switch connected between the first switch and an output terminal,

wherein the second switch is connected to the first switch at a first node;

a third switch connected between the output terminal and a fourth switch, wherein

the third switch is connected to the fourth switch at a second node and the fourth switch is connected to a ground;

an inductor coupled to the output terminal, and connected between the output terminal and a load; and

a capacitor having a first terminal and a second terminal, the first terminal directly connected to the first node and the second terminal directly connected to the second node, the capacitor arranged to be coupled to a power supply through a first transistor and a second transistor such that when the first and second transistors are simultaneously in a conductive state, the first terminal is electrically connected to the power supply and the second terminal is electrically connected to the power supply.

6 . The electronic component of claim 5 , wherein the first, the second, the third and the fourth switches are formed on a single silicon-based die.

7 . The electronic component of claim 5 , further comprising a controller comprising:

circuitry configured to control energy flowing through the first, the second, the third and the fourth switches.

8 . The electronic component of claim 7 , wherein each of the first, the second, the third and the fourth switches includes a gate terminal coupled to the controller.

9 . A circuit comprising:

circuitry configured to control energy flowing through a plurality of serially connected switches that are coupled between an input terminal and a ground, the plurality of serially connected switches further coupled to an output terminal, wherein the plurality of serially connected switches includes:

a first switch connected to the input terminal;

a second switch connected between the first switch and the output terminal, the second switch being connected to the first switch at a first node;

a third switch connected between the output terminal and a fourth switch, the third switch being connected to the fourth switch at a second node and the fourth switch being connected to the ground;

an inductor coupled between the output terminal and a load; and

a capacitor having a first terminal and a second terminal, the first terminal directly connected to the first node and the second terminal directly connected to the second node, the capacitor arranged to be coupled to a power supply through a first transistor and a second transistor such that when the first and second transistors are simultaneously in a conductive state, the first terminal is electrically connected to the power supply and the second terminal is electrically connected to the power supply.

10 . The circuit of claim 9 , wherein the plurality of serially connected switches are formed on a single silicon-based die.

11 . The circuit of claim 9 , further comprising a controller, wherein the controller is arranged to regulate a voltage at the load by controlling the first, the second, the third and the fourth switches.

12 . The circuit of claim 11 , wherein each of the plurality of serially connected switches includes a gate terminal coupled to the controller.

13 . The circuit of claim 11 , wherein the controller and the plurality of serially connected switches are formed on a single silicon-based die.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2022
From: LIDSKY, DAVID; PHILLIPS, TIMOTHY ALAN
To: EMPOWER SEMICONDUCTOR, INC.
Reel/Frame 062010/0597 →
Continuity (4)
Continuation 16823834 · Mar 19, 2020
Continuation 15689997 · Aug 29, 2017
Continuation 14790536 · Jul 2, 2015
Continuation 14635853 · Mar 2, 2015
References Cited (109)
US 5684688A · Rouaud et al. · 1997 [cited by applicant]
US 6121761A · Herbert · 2000 [cited by applicant]
US 7138994B2 · Cho et al. · 2006 [cited by applicant]
US 8022682B2 · Honda et al. · 2011 [cited by applicant]
US 8427113B2 · Xing et al. · 2013 [cited by applicant]
US 9559541B2 · Cheng · 2017 [cited by examiner]
US 9780656B2 · Lidsky et al. · 2017 [cited by applicant]
US 9780663B2 · Lidsky et al. · 2017 [cited by applicant]
US 10389246B1 · Lidsky et al. · 2019 [cited by applicant]
US 10622890B1 · Lidsky et al. · 2020 [cited by applicant]
US 11146170B2 · Xiong et al. · 2021 [cited by applicant]
US 20010033501A1 · Nebrigic · 2001 [cited by examiner]
US 20030214251A1 · Ichikawa et al. · 2003 [cited by applicant]
US 20040036686A1 · Cho et al. · 2004 [cited by applicant]
US 20040141345A1 · Cheng et al. · 2004 [cited by applicant]
US 20050017699A1 · Stanley · 2005 [cited by applicant]
US 20050099364A1 · Jung et al. · 2005 [cited by applicant]
US 20050190583A1 · Morimoto et al. · 2005 [cited by applicant]
US 20060220629A1 · Saito et al. · 2006 [cited by applicant]
US 20060269014A1 · Li · 2006 [cited by applicant]
US 20070115704A1 · Ito · 2007 [cited by applicant]
US 20080157723A1 · Xing et al. · 2008 [cited by applicant]
US 20080290734A1 · Nishigata · 2008 [cited by applicant]
US 20090033289A1 · Xing · 2009 [cited by examiner]
US 20090102439A1 · Williams · 2009 [cited by examiner]
US 20100194339A1 · Yang · 2010 [cited by examiner]
US 20100244798A1 · Nakatomi et al. · 2010 [cited by applicant]
US 20110018511A1 · Carpenter et al. · 2011 [cited by applicant]
US 20110044077A1 · Nielsen · 2011 [cited by examiner]
US 20110169340A1 · Straayer · 2011 [cited by applicant]
US 20110316502A1 · Tang et al. · 2011 [cited by applicant]
US 20130002215A1 · Ikeda et al. · 2013 [cited by applicant]
US 20130021011A1 · Okuda et al. · 2013 [cited by applicant]
US 20130119961A1 · Okuda et al. · 2013 [cited by applicant]
US 20130127523A1 · Vereb et al. · 2013 [cited by applicant]
US 20130207625A1 · Futamura · 2013 [cited by applicant]
US 20130343103A1 · Takizawa · 2013 [cited by applicant]
US 20140001856A1 · Agamy et al. · 2014 [cited by applicant]
US 20140211520A1 · Zhang et al. · 2014 [cited by applicant]
US 20140232364A1 · Thomas · 2014 [cited by examiner]
US 20140266135A1 · Zhak et al. · 2014 [cited by applicant]
US 20140354349A1 · Liu et al. · 2014 [cited by applicant]
US 20140361755A1 · Tateishi et al. · 2014 [cited by applicant]
US 20140375291A1 · Tomasz et al. · 2014 [cited by applicant]
US 20140376287A1 · Narimani et al. · 2014 [cited by applicant]
US 20150061382A1 · Roessler · 2015 [cited by applicant]
US 20150061613A1 · Kondou · 2015 [cited by applicant]
US 20150091544A1 · Jayaraj et al. · 2015 [cited by applicant]
US 20150244262A1 · Ouyang · 2015 [cited by applicant]
US 20150270770A1 · Schroeder · 2015 [cited by applicant]
US 20150277460A1 · Liu · 2015 [cited by applicant]
US 20150280608A1 · Yoscovich et al. · 2015 [cited by applicant]
US 20150311793A1 · Khayat et al. · 2015 [cited by applicant]
US 20150366007A1 · Gong et al. · 2015 [cited by applicant]
US 20160118886A1 · Zhang et al. · 2016 [cited by applicant]
US 20160170425A1 · Lin · 2016 [cited by applicant]
US 20160190921A1 · Kumar · 2016 [cited by examiner]
US 20160254689A1 · Lee et al. · 2016 [cited by applicant]
US 20160254746A1 · Lerdworatawee · 2016 [cited by examiner]
US 20160261185A1 · Lidsky et al. · 2016 [cited by applicant]
US 20160261189A1 · Lidsky et al. · 2016 [cited by applicant]
US 20160344214A1 · Petersen et al. · 2016 [cited by applicant]
US 20170237339A1 · Young · 2017 [cited by examiner]
US 20170250607A1 · Zhak et al. · 2017 [cited by applicant]
US 20170338735A1 · Alarcon-Cot et al. · 2017 [cited by applicant]
WO 2012074967A1 · 2012 [cited by applicant]
U.S. Appl. No. 14/635,853, “First Action Interview Office Action Summary”, Jun. 3, 2015, 2 pages. [cited by applicant]
U.S. Appl. No. 14/635,853, “Non-Final Office Action”, Jun. 3, 2015, 18 pages. [cited by applicant]
U.S. Appl. No. 14/635,853, “Notice of Allowance”, Nov. 17, 2015, 12 pages. [cited by applicant]
U.S. Appl. No. 14/790,536, “Non-Final Office Action”, Nov. 18, 2016, 16 pages. [cited by applicant]
U.S. Appl. No. 14/790,536, “Notice of Allowance”, May 31, 2017, 15 pages. [cited by applicant]
U.S. Appl. No. 14/790,536, “Supplemental Notice of Allowance”, Jun. 21, 2017, 2 pages. [cited by applicant]
U.S. Appl. No. 15/046,145, “Non-Final Office Action”, Dec. 1, 2016, 18 pages. [cited by applicant]
U.S. Appl. No. 15/046,145, “Notice of Allowance”, May 30, 2017, 10 pages. [cited by applicant]
U.S. Appl. No. 15/046,145, “Supplemental Notice of Allowance”, Jul. 13, 2017, 2 pages. [cited by applicant]
U.S. Appl. No. 15/689,698, “Corrected Notice of Allowability”, Jun. 12, 2019, 5 pages. [cited by applicant]
U.S. Appl. No. 15/689,698, “Corrected Notice of Allowability”, May 30, 2019, 8 pages. [cited by applicant]
U.S. Appl. No. 15/689,698, “First Action Interview Office Action Summary”, Jun. 27, 2018, 5 pages. [cited by applicant]
U.S. Appl. No. 15/689,698, “First Action Interview Pilot Program Pre-Interview Communication”, Mar. 29, 2018, 3 pages. [cited by applicant]
U.S. Appl. No. 15/689,698, “Notice of Allowance”, Apr. 4, 2019, 15 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Advisory Action”, Dec. 27, 2018, 5 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Advisory Action”, Feb. 13, 2019, 5 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Advisory Action”, Sep. 11, 2019, 3 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Corrected Notice of Allowability”, Dec. 27, 2019, 2 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Final Office Action”, Aug. 31, 2018, 14 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Final Office Action”, Jun. 13, 2019, 13 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “First Action Interview Office Action Summary”, May 31, 2018, 5 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “First Action Interview Pilot Program Pre-Interview Communication”, Mar. 26, 2018, 3 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Non-Final Office Action”, Mar. 21, 2019, 13 pages. [cited by applicant]
U.S. Appl. No. 15/689,997, “Notice of Allowance”, Dec. 4, 2019, 11 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Advisory Action”, Jul. 12, 2022, 3 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Corrected Notice of Allowability”, Sep. 28, 2022, 7 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Final Office Action”, Jan. 24, 2022, 11 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Final Office Action”, Jan. 29, 2021, 11 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Non-Final Office Action”, Jul. 20, 2021, 10 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Non-Final Office Action”, Jun. 23, 2020, 12 pages. [cited by applicant]
U.S. Appl. No. 16/513,473, “Notice of Allowance”, Sep. 14, 2022, 11 pages. [cited by applicant]
U.S. Appl. No. 16/823,834, “Final Office Action”, Apr. 2, 2021, 9 pages. [cited by applicant]
U.S. Appl. No. 16/823,834, “Final Office Action”, Mar. 10, 2022, 10 pages. [cited by applicant]
U.S. Appl. No. 16/823,834, “Non-Final Office Action”, Oct. 5, 2020, 9 pages. [cited by applicant]
U.S. Appl. No. 16/823,834, “Non-Final Office Action”, Oct. 8, 2021, 9 pages. [cited by applicant]
U.S. Appl. No. 16/823,834, “Notice of Allowance”, Sep. 6, 2022, 14 pages. [cited by applicant]
Kesarwani, et al., “Resonant-Switched Capacitor Converters for Chip-Scale Power Delivery: Design and Implementation”, IEEE Transactions on Power Electronics, vol. 30, No. 12, 2013, 7 pages. [cited by applicant]
Kim, et al., “A fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS”, IEEE Journal of Solid State Circuits vol. 47, No. 1, Jan. 2012, pp. 206-219. [cited by applicant]
Stauth, et al., “Resonant Switched Capacitor Converters for High-Density Power Delivery”, Thayer School of Engineering at Dartmouth, 2014, pp. 1-23. [cited by applicant]
Yousefzadeh, et al., “Three-Level Buck Converter for Envelope Tracking Applications”, IEEE Transactions on Power Electronics, vol. 21, No. 2, Mar. 2006, pp. 549-552. [cited by applicant]
Office Action in U.S. Appl. No. 18/065,552, mailed Apr. 25, 2024, 12 pages. [cited by applicant]
Final Office Action in U.S. Appl. No. 18/065,552, mailed Aug. 29, 2024, 12 pages. [cited by applicant]
Notice of Allowance dated Jul. 22, 2025 for U.S. Appl. No. 18/065,552 (pp. 1-9). [cited by applicant]