IP Library › Granted Patent US 12,556,836
Granted Patent B2
US 12,556,836 · App. 18/565,229 · Granted Feb 17, 2026

Semiconductor integrated circuit, electronic device, and method for controlling semiconductor integrated circuit

Inventors: Ushio Mameuda (Kanagawa, JP); Junichiro Shirai (Kanagawa, JP); Takashi Nakamura (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N25/709H04N25/76
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Quick Facts
Patent No.
US 12,556,836
App. No.
18/565,229
Granted
Feb 17, 2026
Kind
B2
Abstract

Signal quality is improved in a semiconductor integrated circuit provided with a driver. The semiconductor integrated circuit includes a driver circuit, an adjustment circuit, and a control circuit. In this semiconductor integrated circuit, the driver outputs an output signal from an output node. The adjustment circuit is provided with an adjustment-side termination resistor whose one end is connected to the output node and an adjustment transistor connected to the other end of the adjustment-side termination resistor. The control circuit controls a gate voltage of the adjustment transistor to a value corresponding to a measured temperature.

Claims (48)

1 . A semiconductor integrated circuit comprising:

a driver that outputs an output signal from an output node;

an adjustment circuit provided with an adjustment-side termination resistor whose one end is connected to the output node and an adjustment transistor connected to another end of the adjustment-side termination resistor; and

a control circuit that controls a gate voltage of the adjustment transistor to a value corresponding to a measured temperature.

2 . The semiconductor integrated circuit according to claim 1 , wherein

the adjustment transistor includes a positive-side adjustment transistor and a negative-side adjustment transistor,

the gate voltage includes a positive-side voltage and a negative-side voltage, and

the control circuit supplies a voltage, which is higher as the temperature is higher, to a gate of the positive adjustment transistor as the positive-side voltage and supplies a voltage, which is lower as the temperature is higher, to a gate of the negative adjustment transistor as the negative-side voltage.

3 . The semiconductor integrated circuit according to claim 1 , wherein the control circuit supplies a voltage, which is higher as the temperature is higher, to a gate of the adjustment transistor.

4 . The semiconductor integrated circuit according to claim 1 , wherein the control circuit supplies a voltage, which is lower as the temperature is higher, to a gate of the adjustment transistor.

5 . The semiconductor integrated circuit according to claim 1 , wherein

the adjustment circuit includes a plurality of adjustment units commonly connected to the output node, and

the adjustment transistor and the adjustment-side termination resistor are arranged in each of the plurality of adjustment units.

6 . The semiconductor integrated circuit according to claim 5 , wherein

the control circuit further controls a number of units to be driven among the plurality of adjustment units.

7 . The semiconductor integrated circuit according to claim 1 , further comprising

a power-supply-side regulator that suppresses a fluctuation of a power supply voltage of each of the driver and the adjustment circuit.

8 . The semiconductor integrated circuit according to claim 1 , further comprising

a ground-side regulator that suppresses a fluctuation of a ground voltage of each of the driver and the adjustment circuit.

9 . The semiconductor integrated circuit according to claim 1 , further comprising:

a power-supply-side regulator that suppresses a fluctuation of a power supply voltage of each of the driver and the adjustment circuit; and

a ground-side regulator that suppresses a fluctuation of a ground voltage of each of the driver and the adjustment circuit.

10 . The semiconductor integrated circuit according to claim 1 , wherein

the driver receives an input of a differential signal as an input signal, and

the driver outputs a differential signal as the output signal on a basis of the input signal.

11 . The semiconductor integrated circuit according to claim 1 , wherein

the driver includes a plurality of driver units, and

a predetermined number of driver units among the plurality of driver units are driven in accordance with a predetermined control signal.

12 . The semiconductor integrated circuit according to claim 11 , wherein

each of the plurality of driver units includes:

a p-channel metal oxide semiconductor (pMOS) transistor and an n-channel MOS (nMOS) transistor which are connected in series between a power supply node and a ground node; and

a driver-side termination resistor inserted between the output node and a connection node between the pMOS transistor and the nMOS transistor.

13 . The semiconductor integrated circuit according to claim 11 , wherein

each of the plurality of driver units includes:

a pair of nMOS transistors connected in series between a power supply node and a ground node; and

a driver-side termination resistor inserted between the output node and a connection node of the pair of nMOS transistors.

14 . The semiconductor integrated circuit according to claim 11 , wherein

each of the plurality of driver units includes:

a pair of pMOS transistors connected in series between a power supply node and a ground node; and

a driver-side termination resistor inserted between the output node and a connection node of the pair of pMOS transistors.

15 . An electronic device comprising:

a driver that outputs an output signal from an output node;

an adjustment circuit provided with an adjustment-side termination resistor whose one end is connected to the output node and an adjustment transistor connected to another end of the adjustment-side termination resistor;

a control circuit that controls a gate voltage of the adjustment transistor to a value corresponding to a measured temperature; and

a reception circuit that receives the output signal.

16 . A method for controlling a semiconductor integrated circuit, the method comprising:

a procedure in which a driver outputs an output signal from an output node; and

a control procedure in which a control circuit controls a gate voltage of an adjustment transistor in an adjustment circuit to a value corresponding to a measured temperature, the adjustment circuit being provided with an adjustment-side termination resistor whose one end is connected to the output node and the adjustment transistor connected to another end of the adjustment-side termination resistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2023
From: MAMEUDA, USHIO; SHIRAI, JUNICHIRO; NAKAMURA, TAKASHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 065699/0152 →
Priority Claims (1)
JP 2021-096258 · Jun 9, 2021 · national
Continuity (1)
Related Publication 20240292126A1 · Aug 29, 2024
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