Semiconductor package structure
A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.
1 . A semiconductor device, comprising:
a first wafer comprising:
a deep trench capacitor in a substrate;
a first inter-layer dielectric (ILD) layer on the deep trench capacitor;
a first inter-metal dielectric (IMD) layer on the first ILD layer;
a second metal interconnection in the first ILD layer and the first IMD layer;
a second wafer bonded to the first wafer, wherein the second wafer comprises:
a first active device on a first silicon-on-insulator (SOI) substrate;
a second ILD layer on the first active device;
a second IMD layer on the second ILD layer;
a first metal interconnection in the second ILD layer and the second IMD layer and connected to the first active device and the deep trench capacitor; and
a third metal interconnection connected to the first metal interconnection and penetrating through the first SOI substrate.
2 . The semiconductor device of claim 1 , wherein the first IMD layer contacts the second IMD layer.
3 . The semiconductor device of claim 1 , wherein the first metal interconnection contacts the second metal interconnection.
4 . The semiconductor device of claim 1 , further comprising:
a dielectric layer on the first SOI substrate; and
the third metal interconnection in the dielectric layer, the first SOI substrate, and the second ILD layer.
5 . The semiconductor device of claim 4 , wherein the first metal interconnection contacts the third metal interconnection.
6 . The semiconductor device of claim 5 , further comprising:
a third wafer bonded to the second wafer, wherein the third wafer comprises:
a second active device on a second SOI substrate;
a third ILD layer on the second active device;
a third IMD layer on the third ILD layer; and
a fourth metal interconnection in the third IMD layer and connected to the third metal interconnection.
7 . The semiconductor device of claim 6 , wherein the third IMD layer contacts the dielectric layer.
8 . A semiconductor device, comprising:
a first wafer on top of a packaging substrate, wherein the first wafer comprises a deep trench capacitor;
a second wafer on top of the packaging substrate and adjacent to the first wafer; and
a third wafer on the second wafer, wherein the second wafer and the third wafer are connected by direct bond interconnects.
9 . The semiconductor device of claim 8 , wherein the first wafer comprise:
the deep trench capacitor in a substrate;
a first inter-layer dielectric (ILD) layer on the deep trench capacitor; and
a first metal interconnection in the first ILD layer;
a first redistribution layer (RDL) between the first ILD and the packaging substrate; and
a first bump connecting the first RDL and the packaging substrate.
10 . The semiconductor device of claim 9 , wherein the second wafer comprises:
a first active device on a first silicon-on-insulator (SOI) substrate;
a second interlayer dielectric (ILD) layer on the first active device;
a first inter-metal dielectric (IMD) layer on the second ILD layer;
a second redistribution layer (RDL) between the first SOI substrate and the packaging substrate;
a second metal interconnection in the second ILD layer, the first IMD layer, and the first SOI substrate and connecting the first active device and the second RDL; and
a second bump connecting the second RDL and the packaging substrate.
11 . The semiconductor device of claim 10 , wherein the third wafer comprises:
a second active device on a second SOI substrate;
a third ILD layer on the second active device;
a second IMD layer on the third ILD layer; and
a third metal interconnection in the second IMD layer and connecting the second active device and the second metal interconnection.
12 . The semiconductor device of claim 8 , wherein the first wafer and the second wafer are on a same level.