Memory device and method of forming the same
Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
1 . A memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack comprises a first dielectric layer, a first source/drain (S/D) layer, a second dielectric layer, and a second S/D layer stacked in order;
a first conductive pillar, penetrating through the layer stack;
a first ferroelectric layer, wrapping the first conductive pillar;
a first channel layer, extending between the layer stack and the first ferroelectric layer to contact a top surface of the substrate, wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar;
a first conductive region, disposed in the substrate, wherein the first conductive region and the first conductive pillar have different materials, and the first conductive region is in contact with the first conductive pillar to form a contact interface at the top surface of the substrate; and
a first connector, electrically connected to the first conductive region by a first electrical path.
2 . The memory device of claim 1 , wherein the first conductive region is disposed directly under and electrically coupled to the first conductive pillar.
3 . The memory device of claim 2 , wherein the first conductive region is in direct contact with a bottom surface of the first conductive pillar.
4 . The memory device of claim 1 , wherein the first conductive region comprises an epitaxially grown semiconductor material.
5 . The memory device of claim 1 , wherein the first conductive region is a doped region with N-type or P-type dopants.
6 . The memory device of claim 1 , wherein a portion of the first S/D layer is exposed by the second dielectric layer and the second S/D layer to form a staircase shaped region.
7 . The memory device of claim 6 , further comprising:
a first contact plug, disposed on the first S/D layer in the staircase shaped region; and
a second contact plug, disposed on the second S/D layer in the staircase shaped region, wherein the first contact plug has a length greater than a length of the second contact plug.
8 . The memory device of claim 1 , further comprising:
a second conductive pillar, disposed aside the first conductive pillar and penetrating through the layer stack;
a second ferroelectric layer, wrapping the second conductive pillar; and
a second channel layer, disposed between the layer stack and the second ferroelectric layer, wherein the second ferroelectric layer is in contact with the second channel layer and the second conductive pillar, and the first and second conductive pillars are electrically independent to each other.
9 . The memory device of claim 8 , further comprising:
a second conductive region directly under and electrically coupled to the second conductive pillar; and
a second connector, electrically connected to the second conductive region by a second electrical path.
10 . The memory device of claim 9 , wherein the first connector and the second connector are electrically independent to each other.
11 . The memory device of claim 8 , wherein the first connector and the second connector are disposed at a bottom surface of the substrate.
12 . A memory device, comprising:
a layer stack disposed on a substrate, wherein the layer stack at least comprises two metal layers separated from each other;
a first gate structure and a second gate structure, penetrating through the layer stack, wherein the two metal layers laterally surround the first and second gate structures, wherein the first gate structure comprises:
a first conductive pillar;
a first ferroelectric layer, wrapping the first conductive pillar; and
a first channel layer, extending between the layer stack and the first ferroelectric layer to contact a top surface of the substrate;
a first conductive region, disposed in the substrate directly under the first gate structure, wherein the first conductive region and the first conductive pillar have different materials, and the first conductive region is in contact with the first conductive pillar to form a contact interface at the top surface of the substrate; and
a second conductive region, disposed in the substrate directly under the second gate structure.
13 . The memory device of claim 12 ,
wherein the first ferroelectric layer is in contact with the first channel layer and the first conductive pillar.
14 . The memory device of claim 12 , wherein the second gate structure comprises:
a second conductive pillar;
a second ferroelectric layer, wrapping the second conductive pillar; and
a second channel layer, disposed between the layer stack and the second ferroelectric layer, wherein the second ferroelectric layer is in contact with the second channel layer and the second conductive pillar.
15 . The memory device of claim 12 , further comprising:
a first connector disposed at a bottom surface of the substrate, wherein the first connector is electrically connected to the first conductive region by a first electrical path; and
a second connector disposed at the bottom surface of the substrate, wherein the second connector is electrically connected to the second conductive region by a second electrical path,
wherein the first connector and the second connector are electrically independent to each other.
16 . A memory device, comprising:
a gate pillar, disposed on a substrate;
a first source/drain (S/D) layer, laterally surrounding a lower portion of the gate pillar;
a second S/D layer, laterally surrounding an upper portion of the gate pillar and vertically offset from the first S/D layer;
a channel layer, extending between the first and second S/D layers;
a ferroelectric layer, extending between the channel layer and the gate pillar;
a conductive region, disposed in the substrate, wherein the conductive region and the gate pillar have different materials, and the conductive region is in contact with the gate pillar to form a contact interface at a top surface of the substrate; and
a connector, electrically connected to the conductive region by an electrical path.
17 . The memory device of claim 16 , wherein the conductive region comprises an epitaxially grown semiconductor material.
18 . The memory device of claim 16 , wherein the conductive region is a doped region with N-type or P-type dopants.
19 . The memory device of claim 16 , wherein the gate pillar comprises a conductive material including copper, tungsten, cobalt, aluminum, tungsten nitride, rhuthenium, silver, gold, rhodium, molybdenum, nickel, cadmium, zinc, or a combination thereof.
20 . The memory device of claim 16 , wherein the channel layer comprises a metal oxide including indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tungsten oxide (IWO), tungsten oxide (WO), tantalum oxide (TaO), and molybdenum oxide (MoO), or a combination thereof.