Gate-all-around integrated structures having gate height reduction and dielectric capping material with shoulder portions inside gate stack
Gate-all-around integrated circuit structures having reduced gate height structures and subfins, and method of fabricating gate-all-around integrated circuit structures having reduced gate height structures, are described. For example, an integrated circuit structure includes a plurality of horizontal nanowires above a subfin, and an isolation structure on either side of the subfin. A gate stack is over the plurality of nanowires, around individual nanowires, and over the subfin. Gate spacers are on either side of the gate stack, and a dielectric capping material is inside the gate spacers with shoulder portions inside the gate stack.
1 . An integrated circuit structure, comprising:
a plurality of nanowires above a subfin;
an isolation structure on either side of the subfin;
a gate stack over the plurality of nanowires, around individual nanowires, and over the subfin;
gate spacers on either side of the gate stack; and
a dielectric capping material inside the gate spacers with shoulder portions present inside the gate stack.
2 . The integrated circuit structure of claim 1 , wherein integrated circuit structure has a reduced gate height compared to another integrated circuit structure having the dielectric capping material present inside the gate stack.
3 . The integrated circuit structure of claim 1 , wherein epitaxial source or drain structures are included at first and second ends of the plurality of nanowires.
4 . The integrated circuit structure of claim 3 , wherein internal gate spacers are on either side of the gate stack between the gate stack and the epitaxial source or drain structures.
5 . An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires above a subfin, wherein the subfin has a maximum height and a maximum width with a maximum height to maximum width ratio of less than 3:1;
an isolation structure on either side of the subfin;
a gate stack over the vertical arrangement of horizontal nanowires;
gate spacers on either side of the gate stack; and
a dielectric capping material inside the gate spacers with shoulder portions inside the gate stack.
6 . The integrated circuit structure of claim 5 , wherein integrated circuit structure has a reduced gate height compared to another integrated circuit structure having the dielectric capping material present inside the gate stack.
7 . The integrated circuit structure of claim 5 , wherein epitaxial source or drain structures are included at first and second ends of the vertical arrangement of horizontal nanowires.
8 . The integrated circuit structure of claim 7 , wherein internal gate spacers are on either side of the gate stack between the gate stack and the epitaxial source or drain structures.
9 . A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of nanowires above a subfin;
an isolation structure on either side of the subfin;
a gate stack over the plurality of nanowires, around individual nanowires, and over the subfin;
gate spacers on either side of the gate stack; and
a dielectric capping material inside the gate spacers with shoulder portions inside the gate stack.
10 . The computing device of claim 9 , wherein epitaxial source or drain structures are included at first and second ends of the plurality of nanowires.
11 . The computing device of claim 9 , wherein integrated circuit structure has a reduced gate height compared to another integrated circuit structure having the dielectric capping material present inside the gate stack.
12 . The computing device of claim 9 , further comprising:
a memory coupled to the board.
13 . The computing device of claim 9 , further comprising:
a communication chip coupled to the board.
14 . The computing device of claim 9 , wherein the component is a packaged integrated circuit die.