Semiconductor structure and manufacturing method thereof
A semiconductor structure includes an active layer, a first gate insulator layer disposed over the active layer, a first gate layer disposed over the gate insulator layer, at least one charged layer disposed between the first gate insulator layer and the active layer, and a pair of contact structures disposed over the active layer. The at least one charged layer includes an oxide material.
1 . A semiconductor structure, comprising:
an active layer;
a first gate insulator layer disposed over the active layer;
a first gate layer disposed over the first gate insulator layer;
at least one charged layer disposed between the first gate insulator layer and the active layer, wherein the first gate insulator layer and the active layer are disposed at opposite sides of the at least one charged layer, and the at least one charged layer includes an oxide material; and
a pair of contact structures disposed over the active layer.
2 . The semiconductor structure of claim 1 , wherein the at least one charged layer comprises a first charged layer adjacent to the first gate insulator layer and a second charged layer adjacent to the active layer, and the first charged layer includes a semiconductor-like material having a band gap less than 3 eV and the second charged layer includes a dielectric-like material having a band gap greater than 6 eV.
3 . The semiconductor structure of claim 1 , wherein the at least one charged layer comprises a first charged layer adjacent to the first gate insulator layer and a second charged layer adjacent to the active layer, and the first charged layer includes a dielectric-like material having a band gap greater than 6 eV and the second charged layer includes a semiconductor-like material having a band gap less than 3 eV.
4 . The semiconductor structure of claim 1 , wherein the oxide material of the at least one charged layer includes zinc oxide, aluminum oxide, indium oxide, hafnium oxide, zirconium oxide, gallium oxide, lanthanum oxide, yttrium oxide, tantalum oxide or a combination thereof.
5 . The semiconductor structure of claim 1 , wherein the at least one charged layer has an oxygen content higher than an oxygen content of the first gate insulator layer, and the first gate insulator layer and the active layer, respectively physically contact the opposite sides of the at least one charged layer.
6 . The semiconductor structure of claim 1 , wherein the pair of contact structures is located on the at least one charged layer and at opposite sides of the first gate layer and the first gate insulator layer.
7 . The semiconductor structure of claim 6 , further comprising an interlayer dielectric layer surrounding the first gate layer, the first gate insulator layer, and the pair of contact structures.
8 . The semiconductor structure of claim 1 , wherein the pair of contact structures is located above the at least one charged layer, the first gate insulator layer, and the first gate layer.
9 . The semiconductor structure of claim 8 , further comprising an interlayer dielectric layer surrounding the active layer, the at least one charged layer, the first gate insulator layer, the first gate layer, and the pair of contact structures.
10 . The semiconductor structure of claim 1 , further comprising:
a second gate insulator layer disposed over the active layer and between the pair of the contact structures; and
a second gate layer disposed on the second gate insulator layer.
11 . The semiconductor structure of claim 10 , wherein lateral dimensions of the second gate insulator layer and the second gate layer are smaller than lateral dimensions of the first gate insulator layer and the first gate layer.
12 . A semiconductor structure, comprising:
at least one first transistor structure; and
a second transistor structure disposed over the at least one first transistor structure and electrically connected to the at least one first transistor structure through an interconnect structure, comprising:
a semiconductor channel layer;
a multi-layer stack disposed over the semiconductor channel layer, the multi-layer stack comprises a first gate layer, a first gate dielectric layer, a first threshold voltage tuning layer, and a second threshold voltage tuning layer, wherein the first threshold voltage tuning layer is in contact with a surface of the semiconductor channel layer; and
source and drain structures disposed over the semiconductor channel layer.
13 . The semiconductor structure of claim 12 , wherein the first threshold voltage tuning layer includes a first material and the second threshold voltage tuning layer includes a second material, and a band gap of the first material is larger than a band gap of the second material.
14 . The semiconductor structure of claim 12 , wherein the first threshold voltage tuning layer includes a first material and the second threshold voltage tuning layer includes a second material, and a band gap of the first material is smaller than a band gap of the second material.
15 . The semiconductor structure of claim 12 , wherein a thickness of the first threshold voltage tuning layer is substantially the same as a thickness of the second threshold voltage tuning layer.
16 . The semiconductor structure of claim 12 , further comprising a second gate dielectric layer over the multi-layer stack and a second gate layer over the second gate dielectric layer, wherein the second gate dielectric layer and the second gate layer are disposed between the source and drain structures.
17 . A method for forming a semiconductor structure, comprising:
forming an active layer over a semiconductor base;
forming a first gate dielectric layer over the active layer;
forming a first gate layer over the first gate dielectric layer;
forming an interfacial layer between the first gate dielectric layer and the active layer, wherein the first gate dielectric layer and the active layer are disposed at opposite sides of the interfacial layer, and the interfacial layer includes an oxide material;
forming an interlayer dielectric layer over the semiconductor base structure that covers the first gate layer, the first gate dielectric layer, the interfacial layer, and the active layer; and
forming a pair of contact structures extending through the interlayer dielectric layer and in contact with the active layer.
18 . The method of claim 17 , wherein forming the interfacial layer between the first gate dielectric layer and the active layer comprises depositing a first oxide material layer and a second oxide material layer having an oxide material different from that of the first oxide material layer.
19 . The method of claim 17 , wherein forming the interfacial layer between the first gate dielectric layer and the active layer comprises performing a surface treatment process to the first gate dielectric layer.
20 . The method of claim 17 , further comprising forming a second gate dielectric layer on the active layer and a second gate layer on the second gate dielectric layer, and the second gate dielectric layer and the second gate layer are located between the pair of contact structures within the interlayer dielectric layer.