High-speed hardware-based DVFS system using frequency lock loop and on-die voltage controller
A voltage controller circuit is provided for dynamic frequency and voltage scaling. The voltage controller circuit receives an error signal indicating a frequency error and a code error. The frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency. The minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage. The voltage controller circuit calculates a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error, and sends a request to a power management circuit to cause an updated voltage to be supplied to the processor.
1 . A method for dynamic frequency and voltage scaling, comprising:
receiving, by a voltage controller circuit, an error signal indicating a frequency error and a code error, wherein the frequency error indicates a first difference between a target frequency and an actual frequency generated by an oscillator, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency, and wherein the minimum code corresponds to a maximum frequency that the oscillator generates for a processor to safely operate under a given voltage;
calculating, by the voltage controller circuit, a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error; and
sending a request from the voltage controller circuit to a power management circuit to cause an updated voltage to be supplied to the processor.
2 . The method of claim 1 , wherein the voltage correction value calculated by the voltage controller circuit includes the first gain parameter multiplied by the frequency error and the second gain parameter multiplied by the code error.
3 . The method of claim 1 , further comprising:
obtaining a normalized first voltage adjustment by normalizing a product of the first gain parameter and the frequency error to a common scale;
obtaining a normalized second voltage adjustment by normalizing a product of the second gain parameter and the code error to the common scale; and
adding the normalized first voltage adjustment and the normalized second voltage adjustment to obtain the voltage correction value.
4 . The method of claim 1 , further comprising:
calculating respective voltage correction values for a plurality of processors;
selecting one of the respective voltage correction values; and
requesting the power management circuit for voltage correction by the selected one of the respective voltage correction values.
5 . The method of claim 1 , further comprising:
performing a plurality of iterations of the receiving, the calculating, and the sending in response to the target frequency, wherein a first one of the iterations takes a shorter time than subsequent iterations.
6 . The method of claim 1 , further comprising:
sending requests from the voltage controller circuit to the power management circuit at a decreasing rate over a plurality of iterations.
7 . The method of claim 1 , wherein calculating the voltage correction further comprises:
accumulating voltage correction values over a time period in each of a plurality of iterations of the receiving, the calculating, and the sending to obtain an accumulated voltage correction, wherein the time period increases over the iterations until reaching a maximum value.
8 . The method of claim 7 , further comprising:
averaging the accumulated voltage correction to obtain an averaged voltage correction; and
sending the request indicating the averaged voltage correction to the power management circuit.
9 . The method of claim 1 , wherein the first gain parameter and the second gain parameter are tuned at manufacturing time for each of a plurality of processors that are on a same die as the voltage controller circuit.
10 . The method of claim 1 , further comprising:
receiving the target frequency from a scheduler that determines the target frequency of the processor; and
sending the target frequency to a frequency locked loop (FLL) controller, which controls the actual frequency generated by the oscillator.
11 . A system operative to perform dynamic frequency and voltage scaling, comprising:
a power management circuit;
a plurality of processors, each processor coupled to an oscillator operative to generate a clock signal; and
a voltage controller circuit coupled to the plurality of processors, the voltage controller circuit operative to:
receive an error signal indicating a frequency error and a code error, wherein the frequency error indicates a first difference between a target frequency and an actual frequency generated by the oscillator and provided to one of the processors, and the code error indicates a second difference between a minimum code and an actual code with which the oscillator is configured to generate the actual frequency, and wherein the minimum code corresponds to a maximum frequency that the oscillator generates for the processor to safely operate under a given voltage;
calculate a voltage correction value based on the error signal, a first gain parameter for the frequency error, and a second gain parameter for the code error; and
send a request to the power management circuit to cause an updated voltage to be supplied to the processor.
12 . The system of claim 11 , wherein the voltage correction value calculated by the voltage controller circuit includes the first gain parameter multiplied by the frequency error and the second gain parameter multiplied by the code error.
13 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
obtain a normalized first voltage adjustment by normalizing a product of the first gain parameter and the frequency error to a common scale;
obtain a normalized second voltage adjustment by normalizing a product of the second gain parameter and the code error to the common scale; and
add the normalized first voltage adjustment and the normalized second voltage adjustment to obtain the voltage correction value.
14 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
calculate respective voltage correction values for a plurality of processors;
select one of the respective voltage correction values; and
request the power management circuit for voltage correction by the selected one of the respective voltage correction values.
15 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
perform a plurality of iterations of the receiving, the calculating, and the sending in response to the target frequency, wherein a first one of the iterations takes a shorter time than subsequent iterations.
16 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
send requests to the power management circuit at a decreasing rate over a plurality of iterations.
17 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
accumulate voltage correction values over a time period in each of a plurality of iterations of the receiving, the calculating, and the sending to obtain an accumulated voltage correction, wherein the time period increases over the iterations until reaching a maximum value.
18 . The system of claim 17 , wherein the voltage controller circuit is further operative to:
average the accumulated voltage correction to obtain an averaged voltage correction; and
send the request indicating the averaged voltage correction to the power management circuit.
19 . The system of claim 11 , wherein the first gain parameter and the second gain parameter are tuned at manufacturing time for each of a plurality of processors that are on a same die as the voltage controller circuit.
20 . The system of claim 11 , wherein the voltage controller circuit is further operative to:
receive the target frequency from a scheduler that determines the target frequency of the processor; and
send the target frequency to a frequency locked loop (FLL) controller, which controls the actual frequency generated by the oscillator.