Radio frequency signal limiters with diode-enhanced limiting
View Patent ↗Apparatus and methods for RF signal limiters with diode-enhanced limiting are provided. In certain embodiments, an RF signal limiter includes a field-effect transistor (FET) stack electrically connected between an RF signal path and a limiting node, such as ground. The FET stack includes a first or topmost FET having a drain connected to the RF signal path. The gate of the topmost FET is biased through a first gate resistor. The RF signal limiter further includes a first forward enhancement diode having an anode connected to the RF signal path and a cathode connected to the gate of topmost FET.
1 . A radio frequency (RF) signal limiter comprising:
an RF signal path configured to receive an RF signal;
a field-effect transistor (FET) stack electrically connected between the RF signal path and a limiting node, wherein the FET stack includes a first FET having a drain connected to the RF signal path and a second FET in series with the first FET;
a first gate resistor connected between a control terminal and a gate of the first FET;
a second gate resistor connected between the control terminal and a gate of the second FET;
a first reverse enhancement diode having an anode connected to the limiting node and a cathode connected to the gate of the second FET; and
a first forward enhancement diode having an anode connected to the RF signal path and a cathode connected to the gate of the first FET.
2 . The RF signal limiter of claim 1 , further comprising a second reverse enhancement diode having an anode connected to the source of the first FET and a cathode connected to the gate of the first FET, and a second forward enhancement diode having an anode connected to the drain of the second FET and a cathode connected to the gate of the second FET.
3 . The RF signal limiter of claim 2 , wherein the FET stack further include a third FET between the first FET and the second FET, the RF signal limiter further comprising a third gate resistor connected between the control terminal and a gate of the third FET, a third forward enhancement diode having an anode connected to a drain of the third FET and a cathode connected to the gate of the third FET, and a third reverse enhancement diode having an anode connected to a source of the third FET and a cathode connected to the gate of the third FET.
4 . The RF signal limiter of claim 1 , wherein the FET stack further comprises a third FET between the first FET and the second FET, the RF signal limiter further comprising a second reverse enhancement diode having an anode connected to a source of the third FET and a cathode connected to the gate of the first FET.
5 . The RF signal limiter of claim 4 , further comprising a second forward enhancement diode having an anode connected to a drain of the third FET and a cathode connected to the gate of the second FET.
6 . The RF signal limiter of claim 5 , further comprising a third gate resistor connected between the control terminal and a gate of the third FET, a third forward enhancement diode having an anode connected to the drain of the first FET and a cathode connected to the gate of the third FET, and a third reverse enhancement diode having an anode connected to a source of the second FET and a cathode connected to the gate of the third FET.
7 . The RF signal limiter of claim 1 , wherein the first forward enhancement diode is a diode-connected FET.
8 . The RF signal limiter of claim 1 , further comprising a digital buffer configured to set the control terminal to a first voltage level in a first state of an enable signal, and to a second voltage level in a second state of the enable signal.
9 . The RF signal limiter of claim 1 , wherein the first FET comprises a silicon-on-insulator (SOI) transistor.
10 . A radio frequency (RF) communication system comprising:
an RF amplifier configured to amplify an RF signal received from an RF signal path; and
an RF signal limiter comprising:
a field-effect transistor (FET) stack electrically connected between the RF signal path and a limiting node, wherein the FET stack includes a first FET having a drain connected to the RF signal path and a second FET in series with the first FET;
a first gate resistor connected between a control terminal and a gate of the first FET;
a second gate resistor connected between the control terminal and a gate of the second FET;
a first reverse enhancement diode having an anode connected to the limiting node and a cathode connected to the gate of the second FET; and
a first forward enhancement diode having an anode connected to the RF signal path and a cathode connected to the gate of the first FET.
11 . The RF communication system of claim 10 , wherein the RF signal limiter further comprises a second reverse enhancement diode having an anode connected to the source of the first FET and a cathode connected to the gate of the first FET, and a second forward enhancement diode having an anode connected to the drain of the second FET and a cathode connected to the gate of the second FET.
12 . The RF communication system of claim 11 , wherein the FET stack further comprises a third FET between the first FET and the second FET, the RF signal limiter further comprising a third gate resistor connected between the control terminal and a gate of the third FET, a third forward enhancement diode having an anode connected to a drain of the third FET and a cathode connected to the gate of the third FET, and a third reverse enhancement diode having an anode connected to a source of the third FET and a cathode connected to the gate of the third FET.
13 . The RF communication system of claim 10 , wherein the FET stack further comprises a third FET between the first FET and the second FET, the RF signal limiter further comprising a second reverse enhancement diode having an anode connected to a source of the third FET and a cathode connected to the gate of the first FET.
14 . The RF communication system of claim 13 , further comprising a second forward enhancement diode having an anode connected to a drain of the third FET and a cathode connected to the gate of the second FET.
15 . The RF communication system of claim 14 , further comprising a third gate resistor connected between the control terminal and a gate of the third FET, a third forward enhancement diode having an anode connected to the drain of the first FET and a cathode connected to the gate of the third FET, and a third reverse enhancement diode having an anode connected to a source of the second FET and a cathode connected to the gate of the third FET.
16 . The RF communication system of claim 10 , wherein the first forward enhancement diode is a diode-connected FET.
17 . The RF communication system of claim 10 , further comprising a digital buffer configured to set the control terminal to a first voltage level in a first state of an enable signal, and to a second voltage level in a second state of the enable signal.
18 . A method of radio frequency (RF) signal limiting, the method comprising:
receiving an RF signal on an RF signal path;
limiting the RF signal using a field-effect transistor (FET) stack electrically connected between the RF signal path and a limiting node, wherein the FET stack includes a first FET having a drain connected to the RF signal path and a second FET in series with the first FET;
biasing the FET stack using a control terminal that is connected to a gate of the first FET through a first gate resistor and to a gate of the second FET through a second gate resistor;
modulating a voltage of the gate of the second FET using a first reverse enhancement diode having an anode connected to the limiting node and a cathode connected to the gate of the second FET; and
modulating a voltage of the gate of the first FET using a first forward enhancement diode having an anode connected to the RF signal path and a cathode connected to the gate of the first FET.
19 . The method of claim 18 , wherein the first reverse enhancement diode is a diode-connected FET.
20 . The method of claim 18 , wherein the first forward enhancement diode is a diode-connected FET.