IP Library › Granted Patent US 12,573,760
Granted Patent B2
US 12,573,760 · App. 18/311,959 · Granted Mar 10, 2026

Antenna tuning circuit

Inventors: Chenhui Niu (San Jose, CA); David Edward Reed (Calhan, CO)
Assignee: Qorvo US, Inc.
H01Q9/0442H01Q5/335
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,573,760
App. No.
18/311,959
Granted
Mar 10, 2026
Kind
B2
Abstract

An antenna tuning circuit is disclosed. The antenna tuning circuit is configured to make multiple estimates on an antenna impedance at an antenna port and determine an optimum tuning state for antenna tuning based on the antenna impedance estimates. The antenna tuning circuit may be further configured according to various embodiments of the present disclosure to minimize impedance estimation error, reduce magnitude and/or phase disturbance during antenna tuning, and extrapolate antenna impedance estimates for both transmit and receive frequencies. As a result, the antenna tuning circuit can accomplish autonomous antenna tuning optimization to thereby improve transmit and receive performance in a wireless communication device.

Claims (38)

1 . An antenna tuning circuit comprising:

an impedance tuner circuit coupled to an antenna port; and

a control circuit configured to:

receive one or more input impedances measured at an input of the impedance tuner circuit, each of the one or more measured input impedances corresponding to a respective one of one or more selected tuning states among a plurality of tuning states associated with the impedance tuner circuit;

make one or more estimates of an antenna impedance presenting at the antenna port based on the one or more measured input impedances, respectively;

determine an optimum tuning state among the plurality of tuning states based on the one or more estimates of the antenna impedance; and

configure the impedance tuner circuit based on the determined optimum tuning state to thereby match the antenna impedance presenting at the antenna port.

2 . The antenna tuning circuit of claim 1 , further comprising an impedance sensor coupled to the input of the impedance tuner circuit and configured to measure the one or more input impedances each corresponding to the respective one of the one or more selected tuning states.

3 . The antenna tuning circuit of claim 2 , further comprising a second impedance sensor coupled between an output of the impedance tuner circuit and the antenna port, the second impedance sensor is configured to measure a power loss at the antenna port to thereby enable the control circuit to optimize the determined optimum tuning state.

4 . The antenna tuning circuit of claim 2 , wherein:

the impedance sensor is further configured to measure the one or more input impedances at one or more transmitting frequencies, respectively; and

the control circuit is further configured to make the one or more estimates of the antenna impedance at the one or more transmitting frequencies, respectively.

5 . The antenna tuning circuit of claim 4 , wherein the control circuit is further configured to extrapolate one or more receiving impedances at one or more receiving frequencies falling outside a measurement range of the impedance sensor.

6 . The antenna tuning circuit of claim 1 , wherein the one or more estimates of the antenna impedance each corresponds to a respective one of one or more error distribution circles each comprising:

a center corresponding to a respective one of the one or more estimates of the antenna impedance; and

a radius corresponding to a respective error vector magnitude (EVM).

7 . The antenna tuning circuit of claim 1 , wherein the control circuit is further configured to determine the optimum tuning state among the plurality of tuning states based on an average of the one or more estimates of the antenna impedance.

8 . The antenna tuning circuit of claim 1 , wherein the control circuit is further configured to control a transfer function of the impedance tuner circuit to limit a magnitude and/or a phase change in a transmit power delivered to the antenna port and/or a receive power received via the antenna port.

9 . The antenna tuning circuit of claim 1 , wherein the control circuit is further configured to determine the optimum tuning state based on an impedance tuner model comprising a static tuner state block and a dynamic tuner state block comprising a pair of programmable automation controller (PAC) blocks.

10 . A method for performing closed loop antenna tuning comprising:

measuring one or more input impedances each corresponding to a respective one of one or more selected tuning states among a plurality of tuning states;

making one or more estimates of an antenna impedance based on the one or more measured input impedances, respectively;

determining an optimum tuning state among the plurality of tuning states based on the one or more estimates of the antenna impedance; and

matching the antenna impedance based on the determined optimum tuning state.

11 . The method of claim 10 , further comprising measuring the one or more input impedances in one or more measurement error circles based on one or more selected tunning states, respectively.

12 . The method of claim 11 , further comprising making the one or more estimates of the antenna impedance in one or more estimation error circles based on the one or more measured input impedances, respectively.

13 . The method of claim 12 , further comprising:

measuring the one or more input impedances at one or more transmitting frequencies, respectively; and

making the one or more estimates of the antenna impedance at the one or more transmitting frequencies, respectively.

14 . The method of claim 13 , further comprising extrapolating one or more receiving impedances at one or more receiving frequencies.

15 . The method of claim 12 , wherein each of the one or more estimation error circles corresponds to a respective one of one or more error distribution circles each comprising:

a center corresponding to a respective one of the one or more estimates of the antenna impedance; and

a radius corresponding to a respective error vector magnitude (EVM).

16 . The method of claim 12 , further comprising averaging the one or more estimates of the antenna impedance to thereby reduce random noise associated with each of the one or more estimates of the antenna impedance.

17 . The method of claim 10 , further comprising determining the optimum tuning state based on an average of the one or more estimates.

18 . The method of claim 10 , further comprising determining the optimum tuning state based on a tuner model comprising a static tuner state block and a dynamic tuner state block comprising a pair of programmable automation controller (PAC) blocks.

19 . The method of claim 10 , further comprising optimizing the determined optimum tuning state based on a measured power loss.

20 . The method of claim 10 , further comprising limiting a magnitude and/or a phase change in a transmit power and/or a receive power.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2023
From: NIU, CHENHUI
To: QORVO US, INC.
Reel/Frame 063716/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2023
From: REED, DAVID EDWARD
To: QORVO US, INC.
Reel/Frame 063531/0215 →
Continuity (3)
Provisional Application 63389166 · Jul 14, 2022
Provisional Application 63340991 · May 12, 2022
Related Publication 20230369767A1 · Nov 16, 2023
References Cited (23)
US 4095186A · Vesel · 1978 [cited by applicant]
US 5187719A · Birgenheier et al. · 1993 [cited by applicant]
US 6859761B2 · Bensky et al. · 2005 [cited by applicant]
US 8737929B2 · Cohen et al. · 2014 [cited by applicant]
US 8869612B2 · Chen et al. · 2014 [cited by applicant]
US 9225507B1 · Lye et al. · 2015 [cited by applicant]
US 9392558B2 · See et al. · 2016 [cited by applicant]
US 9793610B2 · Wehrmann et al. · 2017 [cited by applicant]
US 10056888B2 · Iversen · 2018 [cited by applicant]
US 10599601B1 · Ngo et al. · 2020 [cited by applicant]
US 10680574B1 · Hrivnak et al. · 2020 [cited by applicant]
US 11711107B2 · Iversen et al. · 2023 [cited by applicant]
US 20070296396A1 · Nakahira · 2007 [cited by applicant]
US 20120232471A1 · Chen et al. · 2012 [cited by applicant]
US 20160226429A1 · Lee · 2016 [cited by applicant]
US 20170346178A1 · Shi · 2017 [cited by examiner]
US 20180262257A1 · Greene · 2018 [cited by examiner]
US 20210218430A1 · Han et al. · 2021 [cited by applicant]
US 20210407771A1 · Funk et al. · 2021 [cited by applicant]
Yeo, K.S. et al., “Non-sequential linear CMOS phase detector for CDR applications,” IEEE Proceedings-Circuits, Devices and Systems, vol. 152, No. 6, Dec. 2005, pp. 667-672. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 15/431,933, mailed Apr. 27, 2018, 9 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 17/454,437, mailed Mar. 7, 2023, 9 pages. [cited by applicant]
Extended European Search Report for European Patent Application No. 23172292.7, mailed Oct. 10, 2023, 8 pages. [cited by applicant]