IP Library Granted Patent US 12,573,944
Granted Patent B2
US 12,573,944 · App. 18/437,182 · Granted Mar 10, 2026

Systems and methods for operating PFC circuits in discontinuous/critical conduction modes

Inventor: Milind Gupta (San Jose, CA)
Assignee: Navitas Semiconductor Limited
H02M1/42H02M1/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,573,944
App. No.
18/437,182
Granted
Mar 10, 2026
Kind
B2
Abstract

A method of operating a PFC circuit. The method includes receiving an input voltage at an input terminal, controlling a current in an inductor via a first switch having a drain terminal, a source terminal and a gate terminal, where the inductor is coupled between the input terminal and the drain terminal and where during an on-time of the first switch the current in the inductor increases from substantially zero to a peak, during a first off-time of the first switch the current in the inductor decreases from the peak to substantially zero, and during a second off-time of the first switch the current in the inductor is substantially zero, generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch, and controlling the on-time of the first switch in response to the first reference voltage.

Claims (78)

1 . A method of operating a power factor correction (PFC) circuit, the method comprising:

receiving an input voltage at an input terminal;

controlling a current in an inductor via a first switch having a drain terminal, a source terminal and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal and wherein:

during an on-time of the first switch the current in the inductor increases from substantially zero to a peak;

during a first off-time of the first switch the current in the inductor decreases from the peak to substantially zero; and

during a second off-time of the first switch the current in the inductor is substantially zero;

generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and

controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first and second off-times to the sum of the on-time and the first off-time.

2 . The method of claim 1 , wherein generating the first reference voltage comprises:

generating a first voltage that is proportional to the sum of the on-time and the first off-time of the first switch;

generating a second voltage by comparing the input voltage to a second reference voltage; and

generating the first reference voltage by setting equal the first voltage to the second voltage.

3 . The method of claim 2 , wherein generating the first voltage comprises:

generating a current signal corresponding to the first reference voltage; and

transmitting the current signal to a second switch that is arranged to switch at a switching cycle that is proportional to sum of the on-time and the first off-time of the first switch.

4 . The method of claim 3 , wherein generating the first voltage further comprises:

generating a voltage signal corresponding to the first reference voltage; and

transmitting the voltage signal to a first capacitor coupled to the second switch.

5 . The method of claim 2 , wherein generating the second voltage comprises:

generating an inverse ratio of a square of the input voltage; and

multiplying the inverse ratio of the square of the input voltage to a third voltage that corresponds to the input voltage.

6 . The method of claim 1 , wherein controlling the on-time of the first switch comprises:

generating a sawtooth signal; and

comparing the sawtooth signal to the first reference voltage to generate a control signal for the first switch.

7 . A method of operating a power factor correction (PFC) circuit, the method comprising:

receiving an input voltage at an input terminal;

controlling a current in an inductor via a first switch having a drain terminal, a source terminal and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal and wherein:

during an on-time of the first switch the inductor is charged with a quantity of energy;

during a first off-time of the first switch the quantity of energy is discharged from the inductor; and

during a second off-time of the first switch the inductor remains discharged;

generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and

controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first and second off-times to the sum of the on-time and the first off-time.

8 . The method of claim 7 , wherein generating the first reference voltage comprises:

generating a first voltage that is proportional to the sum of the on-time and the first off-time of the first switch;

generating a second voltage by comparing the input voltage to a second reference voltage; and

generating the first reference voltage by setting equal the first voltage to the second voltage.

9 . The method of claim 8 , wherein generating the first voltage comprises:

generating a current signal corresponding to the first reference voltage; and

transmitting the current signal to a second switch that is arranged to switch at a switching cycle that is proportional to sum of the on-time and the first off-time of the first switch.

10 . The method of claim 9 , wherein generating the first voltage further comprises:

generating a voltage signal corresponding to the first reference voltage; and

transmitting the voltage signal to a first capacitor coupled to the second switch.

11 . The method of claim 9 , wherein the current signal is a first current signal and wherein generating the first current signal comprises:

generating a second current signal, by a transconductance amplifier, corresponding to the first reference voltage; and

generating the first current signal, by a current mirror, corresponding to the second current signal.

12 . The method of claim 8 , wherein generating the second voltage comprises:

generating an inverse ratio of a square of the input voltage; and

multiplying the inverse ratio of the square of the input voltage to a third voltage that corresponds to the input voltage.

13 . The method of claim 7 , wherein controlling the on-time of the first switch comprises:

generating a sawtooth signal; and

comparing the sawtooth signal to the first reference voltage to generate a control signal for the first switch.

14 . A method of operating a power factor correction (PFC) circuit, the method comprising:

receiving an input voltage at an input terminal;

controlling a current in an inductor via a first switch having a drain terminal, a source terminal and a gate terminal, wherein the inductor is coupled between the input terminal and the drain terminal and wherein:

during an on-time of the first switch the inductor is charged to a first energy state;

during a first off-time of the first switch the inductor is discharged to a second energy state; and

during a second off-time of the first switch the inductor remains at the second energy state;

generating a first reference voltage that is inversely proportional to a sum of the on-time and the first off-time of the first switch; and

controlling the on-time of the first switch in response to the first reference voltage such that the on-time is proportional to a ratio of a sum of the on-time and the first and second off-times to the sum of the on-time and the first off-time.

15 . The method of claim 14 , wherein generating the first reference voltage comprises:

generating a first voltage that is proportional to the sum of the on-time and the first off-time of the first switch;

generating a second voltage by comparing the input voltage to a second reference voltage; and

generating the first reference voltage by setting equal the first voltage to the second voltage.

16 . The method of claim 15 , wherein generating the first voltage comprises:

generating a current signal corresponding to the first reference voltage; and

transmitting the current signal to a second switch that is arranged to switch at a switching cycle that is proportional to sum of the on-time and the first off-time of the first switch.

17 . The method of claim 16 , wherein generating the first voltage further comprises:

generating a voltage signal corresponding to the first reference voltage; and

transmitting the voltage signal to a first capacitor coupled to the second switch.

18 . The method of claim 16 , wherein the current signal is a first current signal and wherein generating the first current signal comprises:

generating a second current signal, by a transconductance amplifier, corresponding to the first reference voltage; and

generating the first current signal, by a current mirror, corresponding to the second current signal.

19 . The method of claim 15 , wherein generating the second voltage comprises:

generating an inverse ratio of a square of the input voltage; and

multiplying the inverse ratio of the square of the input voltage to a third voltage that corresponds to the input voltage.

20 . The method of claim 14 , wherein controlling the on-time of the first switch comprises:

generating a sawtooth signal; and

comparing the sawtooth signal to the first reference voltage to generate a control signal for the first switch.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2025
From: GUPTA, MILIND
To: NAVITAS SEMICONDUCTOR LIMITED
Reel/Frame 073165/0362 →
Continuity (1)
Related Publication 20250260312A1 · Aug 14, 2025
References Cited (8)
US 6518738B1 · Wang · 2003 [cited by examiner]
US 8120347B1 · Cao · 2012 [cited by examiner]
US 9584009B2 · Tan · 2017 [cited by examiner]
US 10999905B2 · Eum · 2021 [cited by examiner]
US 12308735B2 · Gupta · 2025 [cited by examiner]
US 20100110739A1 · Nishikawa · 2010 [cited by examiner]
US 20190028022A1 · Kim · 2019 [cited by examiner]
US 20190260289A1 · Leisten · 2019 [cited by examiner]