IP Library › Granted Patent US 12,575,341
Granted Patent B2
US 12,575,341 · App. 17/874,742 · Granted Mar 10, 2026

Method for annealing bonding wafers

Inventors: Patrick Krüger (Frankfurt, DE); Thomas Voss (Frankfurt, DE); Matthias Wietstruck (Frankfurt, DE)
Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / LEIBNIZ-INSTITUT FUR INNOVATIVE MIKRO
H01L21/187H01L21/2007H01L21/324
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Quick Facts
Patent No.
US 12,575,341
App. No.
17/874,742
Granted
Mar 10, 2026
Kind
B2
Abstract

The invention relates to a method for annealing of at least two wafers bonded via low-temperature direct bonding comprising heating the bonded wafers up to a first annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., holding the first annealing temperature in a range of 1 to 4 hours, preferably 1 to 3 hours, cooling down the bonded wafers to room temperature, re-heating the bonded wafers to a second annealing temperature in the range of 100° C. to 500° C., preferably 150° C. to 400° C., even more preferred 150° C. to 200° C., and cooling down the bonded wafers to room temperature.

Claims (18)

1 . A method for annealing of at least two wafers bonded via low-temperature direct bonding comprising the following steps:

heating the bonded wafers up to a first annealing temperature in the range of 100° C. to 500° C.,

holding the first annealing temperature in a range of 1 to 4 hours, cooling down the bonded wafers to room temperature,

re-heating the bonded wafers to a second annealing temperature in the range of 150° C. to 200° C.,

cooling down the bonded wafers to room temperature,

re-heating the bonded wafers to a third annealing temperature in the range of 100° C. to 500° C., and

cooling down the bonded wafers to room temperature.

2 . The method according to claim 1 , further comprising the step of holding the second and/or third annealing temperature in a range of 2 minutes to 1 hours, before cooling down the bonded wafers to room temperature.

3 . The method according to claim 2 , wherein the second and/or third annealing temperature is the same temperature as the first annealing temperature or is higher or lower than the first annealing temperature within a range of +/−50° C.

4 . The method according to claim 3 , wherein heating to the first and/or second and/or third annealing temperature takes place with a rate of at least 50 K/min.

5 . The method according to claim 4 , wherein cooling down after the first and/or second and/or third annealing temperature takes place with a rate of at least 50 K/min.

6 . The method according to claim 5 , wherein the low-temperature direct bonding is a plasma activated bonding process, a surface activated bonding process, a bonding process under ultra-high vacuum (UHV), a bonding process using a surface activation by chemical-mechanical polishing (CMP) or a bonding process using a surface treatment to achieve chemical activation in hydrolysed tetraalkoxysilanes Si(OR) 4 , hydrolysed tetramethoxysilane Si(OCH 3 ) 4 or nitride acid HNO 3 .

7 . The method according to claim 6 , wherein at least one of the wafers comprises silicon, a metal oxide, a metalloid oxide, or is a glass substrate.

8 . The method according to claim 7 , wherein the steps of heating and/or re-heating are performed using a heat plate, a furnace or a heating lamp.

9 . The method according to claim 1 , further comprising the step of holding the second and/or third annealing temperature in a range of 2 minutes to 1 hours before cooling down the bonded wafers to room temperature.

10 . The method according to claim 1 , wherein the second and/or third annealing temperature is the same temperature as the first annealing temperature or is higher or lower than the first annealing temperature within a range of +/−50° C.

11 . The method according to claim 1 , wherein heating to the first and/or second and/or third annealing temperature takes place with a rate of at least 50 K/min.

12 . The method according to claim 1 , wherein cooling down after the first and/or second and/or third annealing temperature takes place with a rate of at least 50 K/min.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2022
From: KRÜGER, PATRICK; VOSS, THOMAS; WIETSTRUCK, MATTHIAS
To: IHP GMBH - INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS / LEIBNIZ-INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
Reel/Frame 060993/0580 →
Priority Claims (1)
EP 21187959 · Jul 27, 2021 · regional
Continuity (1)
Related Publication 20230030354A1 · Feb 2, 2023
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