High performance high-voltage isolators
An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.
1 . A process of forming an integrated circuit comprising:
forming a metal isolation element over a substrate;
forming a metal ring substantially surrounding the metal isolation element;
forming a protective overcoat over the metal isolation element, the protective overcoat extending over the metal ring; and
forming a trench opening that extends through the protective overcoat, the trench opening exposing a top dielectric layer in a ring between the metal isolation element and the metal ring, the trench opening surrounding the metal isolation element.
2 . The process as recited in claim 1 in which forming the metal isolation element and forming the metal ring include forming a layer of aluminum using subtractive etching.
3 . The process as recited in claim 2 in which forming the protective overcoat includes:
forming a dielectric liner over the metal isolation element, the dielectric liner extending over the metal ring; and
forming a dielectric overcoat on the dielectric liner, the dielectric overcoat including a layer of a SiN-related material that is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride.
4 . The process as recited in claim 1 in which forming the metal isolation element and forming the metal ring includes forming a layer of copper using a damascene process.
5 . The process as recited in claim 4 in which forming the protective overcoat includes:
forming a dielectric liner over the metal isolation element, the dielectric liner extending over the metal ring; the dielectric liner including a layer of a SiN-related material that is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride; and
forming a dielectric overcoat on the dielectric liner.
6 . The process as recited in claim 1 in which the metal isolation element is a top metal isolation element and including forming a lower metal isolation element between the top metal isolation element and the substrate.
7 . The process as recited in claim 6 in which forming the top metal isolation element and forming the lower metal isolation element include forming metal plates.
8 . The process as recited in claim 6 in which forming the top metal isolation element and forming the lower metal isolation element include forming metal coils.
9 . The process as recited in claim 1 in which forming the metal ring includes conductively coupling the metal ring to the substrate.
10 . A method of forming an integrated circuit, comprising;
forming an isolation element in a metal layer on a dielectric layer over a semiconductor substrate;
forming a metal ring in the metal layer that substantially surrounds the isolation element;
forming a protective overcoat over the isolation element and the metal ring; and
forming openings in the protective overcoat, including a first opening that exposes the isolation element and a second opening that exposes the dielectric layer between the isolation element and the metal ring.
11 . The method of claim 10 in which forming the isolation element and forming the metal ring include forming a layer of aluminum using subtractive etching.
12 . The method of claim 11 in which forming the protective overcoat includes:
forming a dielectric liner over the isolation element, the dielectric liner extending over the metal ring; and
forming a dielectric overcoat on the dielectric liner, the dielectric overcoat including a layer of a SiN-related material that is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride.
13 . The method of claim 10 in which forming the isolation element and forming the metal ring includes forming a layer of copper using a damascene process.
14 . The method of claim 13 in which forming the protective overcoat includes:
forming a dielectric liner over the isolation element, the dielectric liner extending over the metal ring; the dielectric liner including a layer of a SiN-related material that is selected from the group consisting of silicon nitride, silicon oxynitride, silicon-rich silicon nitride, silicon-rich silicon oxynitride, silicon oxide carbide nitride, and silicon carbide nitride; and
forming a dielectric overcoat on the dielectric liner.
15 . The method of claim 10 in which the isolation element is an upper metal isolation element and includes forming a lower metal isolation element between the upper metal isolation element and the semiconductor substrate.
16 . The method of claim 15 in which forming the upper metal isolation element and forming the lower metal isolation element include forming metal plates.
17 . The method of claim 15 in which forming the upper metal isolation element and the lower metal isolation element include forming metal coils.
18 . The method of claim 10 in which forming the metal ring includes conductively coupling the metal ring to the substrate.
19 . The method of claim 10 in which forming the second opening includes forming a trench that substantially surrounds the isolation element.