Biasing of radio-frequency switches
In some embodiments, a switching circuit can include a first node and a second node, and a plurality of transistors implemented in a stack configuration between the first node and the second node, with each transistor having a source, a drain and a gate, and the transistors being configured to be in an ON state or an OFF state to respectively allow or inhibit passage of a signal between the first and second nodes. The switching circuit can further include a bias circuit configured to bias the transistors from a bias node. The bias circuit can include a gate-gate resistor that couples each pair of neighboring transistors of the plurality of transistors, and a feed node coupled to the bias node, with the feed node being connected directly to the gate of a selected transistor of the plurality of transistors.
1 . A switching circuit comprising:
a first node, a second node, and a ground node;
a series arm including a stack of transistors implemented between the first node and the second node, each transistor having a source, a drain and a gate;
a shunt arm including a stack of transistors implemented between the first node and the ground node, each transistor having a source, a drain and a gate;
a series arm bias circuit including a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the series arm, and a gate-gate resistor that couples each pair of neighboring transistors of the series arm; and
a shunt arm bias circuit including a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the shunt arm, and a gate-gate resistor that couples each pair of neighboring transistors of the shunt arm.
2 . The switching circuit of claim 1 wherein the shunt arm bias circuit further includes a resistor that couples the drain and source of each transistor of the shunt arm.
3 . The switching circuit of claim 1 further comprising a common resistor that couples the bias node of the shunt arm to the feed node of the shunt arm.
4 . The switching circuit of claim 1 wherein each of the plurality of gate-gate resistors of the shunt arm bias circuit has approximately the same resistance value.
5 . The switching circuit of claim 1 wherein the transistors of the shunt arm are implemented as silicon-on-insulator devices.
6 . A switching module comprising:
a packaging substrate configured to receive a plurality of components; and
a switch implemented on the packaging substrate, the switch including a first node, a second node, and a ground node, the switch further including a series arm having a stack of transistors implemented between the first node and the second node, each transistor having a source, a drain and a gate, the switch further including a shunt arm having a stack of transistors implemented between the first node and the ground node, each transistor having a source, a drain and a gate, the switch further including a series arm bias circuit having a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the series arm, and a gate-gate resistor that couples each pair of neighboring transistors of the series arm, the switch further including a shunt arm bias circuit having a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the shunt arm, and a gate-gate resistor that couples each pair of neighboring transistors of the shunt arm.
7 . The switching module of claim 6 wherein substantially all of the switch is implemented on a common die.
8 . The switching module of claim 7 wherein the common die is a silicon-on-insulator die.
9 . The switching module of claim 6 wherein the switching module is an antenna switch module or a front-end module.
10 . A wireless device comprising:
a switch including a first node, a second node, and a ground node, the switch further including a series arm having a stack of transistors implemented between the first node and the second node, each transistor having a source, a drain and a gate, the switch further including a shunt arm having a stack of transistors implemented between the first node and the ground node, each transistor having a source, a drain and a gate, the switch further including a series arm bias circuit having a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the series arm, and a gate-gate resistor that couples each pair of neighboring transistors of the series arm, the switch further including a shunt arm bias circuit having a bias node, a feed node coupled to the bias node and connected directly to the gate of a selected transistor of the shunt arm, and a gate-gate resistor that couples each pair of neighboring transistors of the shunt arm; and
an antenna coupled to the second node and configured to support wireless operation of the wireless device.
11 . The wireless device of claim 10 wherein the switch is part of a switching module in communication with the antenna.
12 . The wireless device of claim 10 wherein the wireless operation includes cellular wireless operation.
13 . The switching circuit of claim 1 wherein the selected transistor of the shunt arm is an end transistor on the side of the ground node.