Solid-state imaging device and electronic equipment
Provided is a solid-state imaging device including a photoelectric conversion section, a first transistor, a floating diffusion layer, a second transistor, a conductive layer, and a wiring layer. The photoelectric conversion section photoelectrically converts incident light and accumulates electric charge. The first transistor transfers the electric charge accumulated in the photoelectric conversion section. The floating diffusion layer retains the electric charge transferred by the first transistor. The second transistor amplifies the electric charge retained in the floating diffusion layer. The conductive layer conducts to the floating diffusion layer. The wiring layer causes capacitive coupling with the conductive layer and conducts to a source of the second transistor.
1 . A solid-state imaging device, comprising:
a photoelectric conversion section configured to:
photoelectrically convert incident light; and
accumulate electric charge obtained based on the conversion;
a first transistor configured to transfer the electric charge accumulated in the photoelectric conversion section;
a floating diffusion layer configured to retain the electric charge transferred by the first transistor;
a second transistor configured to amplify the electric charge retained in the floating diffusion layer;
a conductive layer configured to conduct to the floating diffusion layer;
a wiring layer configured to:
control capacitive coupling with the conductive layer; and
conduct to a source of the second transistor; and
a first plurality of conductive members which includes a second plurality of conductive members and a contact, wherein
the contact extends in a stacking direction and configured to connect the wiring layer to the source of the second transistor, and
the wiring layer is at a distance from the second plurality of conductive members.
2 . The solid-state imaging device according to claim 1 , wherein a potential of the wiring layer varies in conjunction with a potential of the conductive layer.
3 . The solid-state imaging device according to claim 1 , wherein
the wiring layer and the conductive layer are in a same layer, and
an insulating layer is between the wiring layer and the conductive layer.
4 . The solid-state imaging device according to claim 1 , wherein
the wiring layer is in a specific layer,
the specific layer is close to a substrate as compared to the conductive layer, and
the photoelectric conversion section and the floating diffusion layer are on the substrate.
5 . The solid-state imaging device according to claim 1 , wherein the wiring layer surrounds at least a portion of the conductive layer.
6 . The solid-state imaging device according to claim 1 , wherein
the conductive layer includes a first end and a second end,
the first end is connected to the floating diffusion layer, and
the second end is connected to a gate of the second transistor.
7 . The solid-state imaging device according to claim 1 , further comprising:
a third transistor configured to:
switch a charge-voltage conversion gain, or
initialize the electric charge in the floating diffusion layer, wherein at least a portion of the wiring layer is between a gate of
the third transistor and the conductive layer.
8 . The solid-state imaging device according to claim 7 , wherein
the wiring layer, a gate wiring layer connected to the gate of the third transistor, and the conductive layer are in a same layer, and
each of the wiring layer, the gate wiring layer, and the conductive layer is covered with an insulating layer.
9 . The solid-state imaging device according to claim 7 , wherein
the wiring layer and the conductive layer are in different layers in the stacking direction,
the wiring layer and a gate wiring layer connected to the gate of the third transistor are in a same layer, and
each of the wiring layer, the conductive layer, and the gate wiring layer are covered with an insulating layer.
10 . The solid-state imaging device according to claim 7 , wherein
the wiring layer and the conductive layer are in a same layer,
the wiring layer and a gate wiring layer connected to the gate of the third transistor are in different layers in the stacking direction, and
each of the wiring layer, the conductive layer, and the gate wiring layer is covered with an insulating layer.
11 . The solid-state imaging device according to claim 10 , wherein
the gate of the third transistor is in a first layer,
the first layer is in a second layer,
the second layer is close to a substrate as compared to the wiring layer and the conductive layer, and
the photoelectric conversion section and the floating diffusion layer are on the substrate.
12 . The solid-state imaging device according to claim 10 , wherein
the wiring layer and the conductive layer are in a first layer,
the first layer is close to a substrate as compared to the gate wiring layer of the third transistor, and
the photoelectric conversion section and the floating diffusion layer are on the substrate.
13 . The solid-state imaging device according to claim 7 , wherein
the conductive layer and a gate wiring layer of the third transistor are in a same layer,
each of the conductive layer and the gate wiring layer is covered with an insulating layer, and
the wiring layer is in a layer different from the conductive layer and the gate wiring layer of the third transistor.
14 . The solid-state imaging device according to claim 13 , wherein
the wiring layer is in a specific layer,
the specific layer is close to a substrate as compared to the conductive layer and the gate wiring layer of the third transistor, and
the photoelectric conversion section and the floating diffusion layer are on the substrate.
15 . The solid-state imaging device according to claim 1 , further comprising:
a conductive member of the first plurality of conductive members that is in a first layer which is different from the wiring layer and a gate of the second transistor in the stacking direction, wherein
the wiring layer is in a second layer between the gate of the second transistor and the conductive member.
16 . The solid-state imaging device according to claim 1 , further comprising:
a first capacitive element;
a second capacitive element;
a pre-stage circuit configured to:
sequentially generate a specific reset level and a signal level based on an exposure amount, and
control the first capacitive element to retain the generated specific reset level and the second capacitive element to retain the generated signal level;
a selection circuit configured to:
sequentially control to connect the first capacitive element to a specific post-stage node,
control to disconnect both of the first capacitive element and the second capacitive element from the specific post-stage node, and
control to connect the second capacitive element to the specific post-stage node;
a post-stage reset transistor configured to initialize a level of the specific post-stage node in a case where both of the first capacitive element and second capacitive element are disconnected from the specific post-stage node; and
a post-stage circuit configured to:
sequentially read the specific reset level and the signal level from the first capacitive element and the second capacitive element through the specific post-stage node, and
output the read specific reset level and the read signal level, wherein
the pre-stage circuit includes the photoelectric conversion section, the first transistor, the floating diffusion layer, the second transistor, the conductive layer, and the wiring layer.
17 . An electronic equipment, comprising:
a solid-state imaging device configured to output a pixel signal obtained by photoelectric conversion of light incident on a pixel area; and
a signal processing section configured to execute signal processing based on the pixel signal, wherein
the solid-state imaging device includes:
a photoelectric conversion section configured to:
photoelectrically convert incident light, and
accumulate electric charge obtained based on the conversion,
a first transistor configured to transfer the electric charge accumulated in the photoelectric conversion section,
a floating diffusion layer configured to retain the electric charge transferred by the first transistor,
a second transistor configured to amplify the electric charge retained in the floating diffusion layer,
a conductive layer configured to conduct to the floating diffusion layer,
a wiring layer configured to:
control capacitive coupling with the conductive layer, and
conduct to a source of the second transistor, and
a first plurality of conductive members which includes a second plurality of conductive members and a contact, wherein
the contact extends in a stacking direction and configured to connect the wiring layer to the source of the second transistor, and
the wiring layer is at a distance from the second plurality of conductive members.