Semiconductor package including under bump metallization pad
A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.
1 . A method for manufacturing a semiconductor package, comprising:
depositing an under bump metallization (UBM) seed layer on a photoimageable dielectric (PID) release layer;
forming a UBM pad on the UBM seed layer;
etching a portion of the UBM seed layer, thereby forming a UBM seed pattern and exposing a portion of the PID release layer;
depositing a UBM protective layer covering the PID release layer and the UBM pad;
forming a lower passivation layer covering the UBM protective layer;
forming a lower redistribution layer on the lower passivation layer;
mounting a semiconductor chip on the lower redistribution layer;
forming, on the lower redistribution layer, a molding layer surrounding the semiconductor chip;
removing the PID release layer;
removing the UBM seed pattern and a portion of the UBM protective layer, thereby exposing a bottom surface of the UBM pad; and
removing a portion of the UBM pad such that the bottom surface of the UBM pad has a first depth from a bottom surface of the lower passivation layer.
2 . The method according to claim 1 ,
wherein the first depth is between 400 nm and 600 nm.
3 . The method according to claim 1 ,
wherein the forming of the lower redistribution layer comprises:
forming a lower insulating layer on the lower passivation layer;
forming a trench at the lower passivation layer and the lower insulating layer;
forming a lower barrier layer in the trench; and
forming a lower redistribution pattern and a lower conductive via in the trench.
4 . The method according to claim 1 ,
wherein the mounting of the semiconductor chip on the lower redistribution layer comprises:
disposing an inner connecting terminal on the lower redistribution layer;
mounting the semiconductor chip on the inner connecting terminal; and
forming an underfill between the lower redistribution layer and the semiconductor chip.
5 . The method according to claim 1 , further comprising:
forming an upper redistribution layer on the molding layer.
6 . The method according to claim 1 ,
wherein the forming of the molding layer comprises:
disposing a connecting via on the lower redistribution layer; and
forming the molding layer on the lower redistribution layer.
7 . The method according to claim 1 , further comprising:
disposing an outer connecting terminal at the bottom surface of the UBM pad.
8 . The method according to claim 1 ,
wherein a cross-section of the UBM pad has a rectangular shape.
9 . The method according to claim 1 ,
wherein the UBM protective layer comprises Ti.
10 . The method according to claim 1 ,
wherein a thickness of the UBM protective layer is 3 nm or less.
11 . A method for manufacturing a semiconductor package, comprising:
forming an under bump metallization (UBM) pad;
depositing a UBM protective layer covering a side surface and a top surface of the UBM pad;
forming a lower passivation layer covering the UBM protective layer;
forming a lower redistribution layer on the lower passivation layer;
mounting a semiconductor chip on the lower redistribution layer;
forming, on the lower redistribution layer, a molding layer surrounding the semiconductor chip;
removing at least a portion of the UBM pad and forming a recess, such that at least a portion of an inner side surface of the UBM protective layer is exposed by the UBM pad; and
forming an outer connecting terminal connected to a bottom surface of the UBM pad.
12 . The method according to claim 11 ,
wherein the bottom surface of the UBM protective layer and a bottom surface of the lower passivation layer are located on a same level.
13 . The method according to claim 11 ,
wherein the bottom surface of the UBM pad is located on a level higher than the level on which a bottom surface of the lower passivation layer is located.
14 . The method according to claim 11 ,
wherein at least a portion of the outer connecting terminal is located on a level higher than the level on which a lowermost end of the UBM protective layer is located.
15 . The method according to claim 11 ,
wherein the outer connecting terminal is connected to at least the portion of the inner side surface of the UBM protective layer.
16 . The method according to claim 11 ,
Wherein the UBM protective layer comprises Ti.
17 . A method for manufacturing a semiconductor package, comprising:
forming an under bump metallization (UBM) pad;
depositing a UBM protective layer covering a side surface and a top surface of the UBM pad;
forming a lower passivation layer covering the UBM protective layer;
forming a lower redistribution layer including on the lower passivation layer;
removing a portion of the UBM pad such that a bottom surface of the UBM pad has a first depth from a bottom surface of the lower passivation layer; and
forming an outer connecting terminal connected to at least a portion of the bottom surface of the UBM pad,
wherein forming the lower redistribution layer includes forming a lower barrier layer, a lower redistribution pattern and a lower conductive via, and
wherein at least a portion of the lower barrier layer is in contact with at least a portion of an upper surface of the UBM pad.
18 . The method according to claim 17 ,
wherein the bottom surface of the lower passivation layer is coplanar with the bottom surface of the UBM protective layer.
19 . The method according to claim 17 ,
wherein the outer connecting terminal is not in contact with the lower passivation layer.
20 . The method according to claim 19 ,
wherein the outer connecting terminal is a solder ball or a solder bump.