IP Library › Granted Patent US 10,861,814
Granted Patent B2
US 10,861,814 · App. 15/965,981 · Granted Dec 8, 2020

Integrated fan-out packages and methods of forming the same

Inventors: Tzung-Hui Lee (New Taipei, TW); Chen-Hua Yu (Hsinchu, TW); Chi-Ming Tsai (New Taipei, TW); Hung-Jui Kuo (Hsinchu, TW); Ming-Che Ho (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L24/19H01L21/481H01L21/486H01L21/4853H01L21/56H01L21/6835H01L23/3128H01L23/49811H01L23/5389H01L24/25H01L24/73H01L21/568H01L24/20H01L24/24H01L2221/68345H01L2221/68359H01L2221/68372H01L2221/68381H01L2224/18H01L2224/215H01L2224/24101H01L2224/24227H01L2224/25171H01L2224/2919H01L2224/32225H01L2224/73209H01L2224/73259H01L2224/73267H01L2224/83005H01L2224/8385
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Quick Facts
Patent No.
US 10,861,814
App. No.
15/965,981
Granted
Dec 8, 2020
Kind
B2
Abstract

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.

Claims (40)

1. An integrated fan-out package, comprising:

a bump structure comprising:

a metal pad; and

a bump electrically connected to the metal pad;

a dielectric layer extending laterally from a sidewall of the bump; and

a redistribution layer comprising a metal line and a polymer layer encapsulating the metal line, wherein the metal pad is disposed between the metal line and the metal bump, and the metal line is in physical contact with a side surface of the metal pad.

2. The integrated fan-out package of claim 1 , wherein the metal line encapsulates the entire side surface and a top surface of the metal pad.

3. The integrated fan-out package of claim 1 , wherein the bump structure further comprises an intermetallic compound layer between the metal pad and the bump, and the intermetallic compound layer comprises gold (Au).

4. The integrated fan-out package of claim 1 , wherein the bump structure further comprises an intermetallic compound layer that is between the metal pad and the bump and in physical contact with the metal line.

5. The integrated fan-out package of claim 1 , wherein the bump structure further comprises an intermetallic compound layer that is between the metal pad and the bump and extends laterally away from the bump.

6. The integrated fan-out package of claim 3 , further comprising a barrier layer vertically between the intermetallic compound layer and the dielectric layer.

7. The integrated fan-out package of claim 1 , wherein the metal pad comprises nickel, copper or a combination thereof, and a thickness of the metal layer of the redistribution layer is about 0.5 to 5 times a thickness of the metal pad.

8. The integrated fan-out package of claim 3 , wherein the intermetallic compound layer is thicker between the metal pad and the bump while thinner between the dielectric layer and the metal line.

9. The integrated fan-out package of claim 1 , further comprising a through integrated fan-out via electrically connected to the metal line.

10. A method of forming an integrated fan-out package, comprising:

providing a carrier having a dielectric layer and a glue layer formed thereon;

plating a plurality of metal pads on the carrier by using the glue layer as a seed layer;

plating metal lines respectively on the metal pads by using the glue layer as a seed layer, wherein the each of the metal lines is in physical contact with an entire side surface of the corresponding metal pad;

forming a polymer layer encapsulating the metal lines;

removing the carrier; and

forming a plurality of bumps through the polymer layer and electrically connected to the metal pads.

11. The method of claim 10 , further comprising, after forming the polymer layer and before removing the carrier:

forming a plurality of integrated fan-out through vias electrically connected to the metal pads;

placing a semiconductor chip on the carrier aside the integrated fan-out through vias; and

forming a second redistribution layer structure over the semiconductor chip.

12. The method of claim 10 , further comprising forming a barrier layer between the glue layer and the dielectric layer.

13. An integrated fan-out package, comprising:

a semiconductor chip;

a first redistribution layer structure located at a back side of the semiconductor chip; and

a second redistribution layer structure located at a front side of the semiconductor chip,

wherein the first redistribution layer structure comprises a metal pad, a metal layer and a polymer layer, the metal layer is in physical contact with an entire side surface of the metal pad, and the polymer layer encapsulates the metal layer.

14. The integrated fan-out package of claim 13 , wherein the metal layer encapsulates the side surface and a top surface of the metal pad.

15. The integrated fan-out package of claim 13 , further comprising:

a bump located at the back side of the semiconductor chip and electrically connected to the first redistribution layer structure; and

an intermetallic compound layer located between the metal pad and the bump, wherein the intermetallic compound layer comprises gold (Au).

16. The integrated fan-out package of claim 15 , wherein the intermetallic compound layer comprises is an Au—Sn intermetallic compound layer, a Ni—Au—Sn intermetallic compound layer, a Cu—Au—Sn intermetallic compound layer or a combination thereof.

17. The integrated fan-out package of claim 15 , wherein the intermetallic compound layer further extends laterally away from the bump.

18. The integrated fan-out package of claim 15 , wherein an edge of the intermetallic compound layer is substantially aligned with an edge of the metal layer.

19. The integrated fan-out package of claim 15 , wherein the intermetallic compound layer has a non-uniform thickness.

20. The integrated fan-out package of claim 15 , further comprising a barrier layer extending laterally from a sidewall of the bump and in physical contact with the intermetallic compound layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 30, 2018
From: LEE, TZUNG-HUI; YU, CHEN-HUA; TSAI, CHI-MING; KUO, HUNG-JUI; HO, MING-CHE
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 045663/0616 →
Continuity (2)
Provisional Application 62580451 · Nov 2, 2017
Related Publication 20190131269A1 · May 2, 2019
Cited By (3)
US 12,300,639 US 12,581,978 US 12,642,148