IP Library › Granted Patent US 12,585,410
Granted Patent B2
US 12,585,410 · App. 18/816,595 · Granted Mar 24, 2026

Storage device and operating method thereof

Inventors: Hyeongyu Cho (Suwon-si, KR); Inhae Kang (Suwon-si, KR); Sooyun Lee (Suwon-si, KR); Sangwook Yoo (Suwon-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
G06F3/0659G06F3/0604G06F3/0634G06F3/0679
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Quick Facts
Patent No.
US 12,585,410
App. No.
18/816,595
Granted
Mar 24, 2026
Kind
B2
Abstract

A storage device includes a storage controller and a non-volatile memory including a first memory region including first memory cells having a first data retention time and a second memory region including second memory cells having a second data retention time that is shorter than the first data retention time. Based on an erase request being received from a host in a first operation mode, the storage controller determines whether to switch from the first operation mode to a second operation mode. The storage controller programs program data in a memory region selected from the first memory region and the second memory region in the first operation mode, and the storage controller programs the program data in only the first memory region in the second operation mode.

Claims (43)

1 . A storage device comprising:

a storage controller; and

a non-volatile memory including a first memory region including first memory cells having a first data retention time and a second memory region including second memory cells having a second data retention time that is shorter than the first data retention time,

wherein, based on an erase request being received from a host in a first operation mode, the storage controller is configured to determine whether to switch from the first operation mode to a second operation mode,

wherein, the storage controller is configured to program program data in a memory region selected from the first memory region and the second memory region in the first operation mode, and

wherein the storage controller is configured to program the program data in only the first memory region in the second operation mode.

2 . The storage device of claim 1 , wherein the storage controller is configured to switch from the first operation mode to the second operation mode when a capacity of memory blocks of which data is requested to be erased is greater than a reference capacity and to maintain the first operation mode when the capacity is less than or equal to the reference capacity.

3 . The storage device of claim 2 , wherein the reference capacity is a first reference ratio or more of a total capacity of the non-volatile memory.

4 . The storage device of claim 1 , wherein, based on a program request being received from the host in the second operation mode, the storage controller is configured to perform a compaction operation to compress the program data and to program the compressed program data in the first memory region.

5 . The storage device of claim 1 , wherein the storage controller is configured to switch from the first operation mode to the second operation mode when a capacity of memory blocks of which data is requested to be erased is greater than a reference capacity and when a valid page count (VPC) of the non-volatile memory is less than a first reference count, and to maintain the first operation mode when the capacity is less than or equal to the reference capacity or when the VPC is greater than or equal to the first reference count.

6 . The storage device of claim 5 , wherein the reference capacity is a first reference ratio or more of a total capacity of the non-volatile memory, and

wherein the first reference count is less than a second reference ratio of a number of pages included in the non-volatile memory.

7 . The storage device of claim 5 , wherein, in the second operation mode, the storage controller is configured to switch from the second operation mode to the first operation mode based on the VPC being greater than a second reference count that is different from the first reference count, and to maintain the second operation mode when the VPC is less than or equal the second reference count.

8 . The storage device of claim 7 , wherein the reference capacity is a first reference ratio or more of a total capacity of the non-volatile memory,

wherein the first reference count is less than a second reference ratio of a number of pages included in the non-volatile memory, and

wherein the second reference count is a third reference ratio or more of a number of pages included in the first memory region.

9 . The storage device of claim 1 , wherein the first memory cells comprise memory cells that store data of less than n bits (n is a natural number of 2 or more), the second memory cells comprise memory cells that store data of n bits or more.

10 . The storage device of claim 1 , wherein the first memory cells include single level cells (SLC) storing 1-bit data, and the second memory cells include multi-level cells (MLC) storing 2-bit data, triple level cells (TLC) storing 3-bit data, and quad level cells (QLC) storing 4-bit data.

11 . A storage device comprising:

a storage controller; and

a non-volatile memory including a first memory region including first memory cells having a first data retention time and a second memory region including second memory cells having a second data retention time that is less than the first data retention time,

wherein, based on an erase request being received from a host in a first operation mode, the storage controller is further configured to switch from the first operation mode to a second operation mode when a capacity of memory blocks of which data is requested to be erased is greater than a reference capacity and a valid page count (VPC) of the non-volatile memory is less than a first reference count, and to maintain the first operation mode when the capacity is less than or equal to the reference capacity or the VPC is greater than or equal to the first reference count,

wherein, when a program request is received from the host in the first operation mode, the storage controller is configured to program program data in a memory region selected from the first memory region and the second memory region, and

wherein, when the program request is received from the host in the second operation mode, the storage controller is configured to program the program data only in the first memory region.

12 . The storage device of claim 11 , wherein, when the program request is received from the host in the second operation mode, the storage controller is configured to perform a compaction operation on the program data to compress the program data and to program the compressed program data in the first memory region.

13 . The storage device of claim 11 , wherein, in the second operation mode, the storage controller is configured to switch from the second operation mode to the first operation mode based on whether the VPC is greater than a second reference count that is different from the first reference count, and to maintain the second operation mode when the VPC is less than or equal to the second reference count.

14 . The storage device of claim 11 , wherein the first memory cells comprise memory cells that store data of less than n bits (n is a natural number of 2 or more), the second memory cells comprise memory cells that store data of n bits or more.

15 . An operating method of a storage device including a non-volatile memory including a first memory region including first memory cells and a second memory region including second memory cells and a storage controller configured to program data or erase data in the non-volatile memory based on a request received from a host, the operating method comprising:

receiving an erase request from the host in a first operation mode in which the program data is programmed in a memory region selected from the first memory region and the second memory region;

determining whether a capacity of memory blocks of which data is requested to be erased is greater than a reference capacity;

based on the capacity being less than or equal to the reference capacity, maintaining the first operation mode;

based on the capacity being greater than the reference capacity, determining whether a valid page count (VPC) of the non-volatile memory is less than a first reference count;

based on the VPC being greater than or equal to the first reference count, maintaining the first operation mode; and

based on the VPC being less than the first reference count, switching from the first operation mode to a second operation mode in which the program data is programmed only in the first memory region.

16 . The operating method of claim 15 , wherein the reference capacity is a first reference ratio or more of a total capacity of the non-volatile memory, and

wherein the first reference count is less than a second reference ratio of a number of pages included in the non-volatile memory.

17 . The operating method of claim 15 , further comprising, in the second operation mode, performing a compaction operation on the program data to compress the program data and programing the compressed program data in the first memory region.

18 . The operating method of claim 15 , further comprising, in the second operation mode, determining whether the VPC is greater than a second reference count, and switching from the second operation mode to the first operation mode when the VPC is greater than the second reference count; and

maintaining the second operation mode when the VPC is less than or equal to the second reference count.

19 . The operating method of claim 18 , wherein the reference capacity is a first reference ratio or more of a total capacity of the non-volatile memory,

wherein the first reference count is less than a second reference ratio of a number of pages included in the non-volatile memory, and

wherein the second reference count is a third reference ratio or more of a number of pages included in the first memory region.

20 . The operating method of claim 15 , wherein the first memory cells comprise memory cells that store data of less than n bits (n is a natural number of 2 or more), the second memory cells comprise memory cells that store data of n bits or more.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2024
From: CHO, HYEONGYU; KANG, INHAE; LEE, SOOYUN; YOO, SANGWOOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 068415/0863 →
Priority Claims (2)
KR 10-2023-0125010 · Sep 19, 2023 · national
KR 10-2023-0165826 · Nov 24, 2023 · national
Continuity (1)
Related Publication 20250094084A1 · Mar 20, 2025
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