Processor cross-core cache line contention management
Embodiments are for processor cross-core cache line contention management. A computer-implemented method includes sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system and determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches. The computer-implemented method also includes waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches and granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.
1 . A computer-implemented method comprising:
sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system;
determining a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches;
waiting until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches; and
granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.
2 . The computer-implemented method of claim 1 , wherein the cache state change request is received from a higher-level cache of a core of the symmetric multiprocessing system, the at least one of the one or more caches comprises one or more higher-level caches of other cores of the symmetric multiprocessing system, and the cache line is managed by a lower-level cache of the symmetric multiprocessing system.
3 . The computer-implemented method of claim 1 , wherein the cross-invalidate reject response is sent by a core of the symmetric multiprocessing system performing an operation on the cache line.
4 . The computer-implemented method of claim 3 , wherein the core determines the retry delay period based on a predicted amount of time to complete an update of the cache line.
5 . The computer-implemented method of claim 4 , further comprising:
mapping a retry indicator encoded in the cross-invalidate reject response to a retry threshold that defines the retry delay period;
loading a delay counter with the retry delay period; and
running the delay counter until the retry delay period has elapsed.
6 . The computer-implemented method of claim 1 , further comprising:
receiving an early restart command; and
resending the cross-invalidate command prior to the retry delay period elapsing based on the early restart command.
7 . The computer-implemented method of claim 1 , wherein a shorter retry delay value is set based on determining that the cache line is being written, and a longer retry delay value is set based on determining that the cache line is in a locked and protected state.
8 . A system comprising:
a plurality of processors each comprising two or more cores forming a symmetric multiprocessing system;
a cache system; and
a controller coupled to the cache system, the controller configured to:
send a cross-invalidate command to one or more caches of the cache system based on receiving a cache state change request for a cache line;
determine a retry delay based on receiving a cross-invalidate reject response from at least one of the one or more caches;
wait until a retry delay period associated with the retry delay has elapsed to resend the cross-invalidate command to the one or more caches; and
grant the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.
9 . The system of claim 8 , wherein the cache state change request is received from a higher-level cache of a core of the symmetric multiprocessing system, the at least one of the one or more caches comprises one or more higher-level caches of other cores of the symmetric multiprocessing system, and the cache line is managed by a lower-level cache of the symmetric multiprocessing system.
10 . The system of claim 8 , wherein the cross-invalidate reject response is sent by a core of the symmetric multiprocessing system performing an operation on the cache line.
11 . The system of claim 10 , wherein the core determines the retry delay period based on a predicted amount of time to complete an update of the cache line.
12 . The system of claim 11 , wherein the controller is further configured to:
map a retry indicator encoded in the cross-invalidate reject response to a retry threshold that defines the retry delay period;
load a delay counter with the retry delay period; and
run the delay counter until the retry delay period has elapsed.
13 . The system of claim 8 , wherein the controller is further configured to:
receive an early restart command; and
resend the cross-invalidate command prior to the retry delay period elapsing based on the early restart command.
14 . The system of claim 8 , wherein a shorter retry delay value is set based on determining that the cache line is being written, and a longer retry delay value is set based on determining that the cache line is in a locked and protected state.
15 . A computer-implemented method comprising:
sending a cross-invalidate command to one or more caches based on receiving a cache state change request for a cache line in a symmetric multiprocessing system;
determining a ticket identifier based on receiving a cross-invalidate reject response with a ticket code from at least one of the one or more caches;
waiting until a wakeup message associated with the ticket identifier has been received to resend the cross-invalidate command to the one or more caches; and
granting the cache state change request for the cache line based on receiving a cross-invalidate accept response from the one or more caches.
16 . The computer-implemented method of claim 15 , wherein the cache state change request is received from a higher-level cache of a core of the symmetric multiprocessing system, the at least one of the one or more caches comprises one or more higher-level caches of other cores of the symmetric multiprocessing system, and the cache line is managed by a lower-level cache of the symmetric multiprocessing system.
17 . The computer-implemented method of claim 15 , wherein the cross-invalidate reject response is sent by a core of the symmetric multiprocessing system performing an operation on the cache line and the core is configured to generate the ticket code and the wakeup message.
18 . The computer-implemented method of claim 17 , wherein the core is configured to send the wakeup message one or more cycles prior to completion of the operation on the cache line.
19 . The computer-implemented method of claim 17 , wherein the wakeup message is sent a number of cycles early to align with an expected processing delay of the wakeup message.
20 . The computer-implemented method of claim 15 , further comprising:
setting a delay counter to a default value based on receiving the cross-invalidate reject response;
resetting the delay counter based on receiving the wakeup message; and
resending the cross-invalidate command to the one or more caches based on the delay counter reaching a limit prior to receiving the wakeup message.