Multi-port SRAM cell with metal interconnect structures
A memory cell includes a device layer including a plurality of transistors and an interconnect structure disposed over the device layer. Each of the transistors includes a gate structure extending lengthwise in a first direction. The interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer. The bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction. A distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform. The first metal track includes a metal line electrically coupled to an electric ground of the memory cell. The sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.
1 . A memory cell, comprising:
a device layer including a plurality of transistors, wherein each of the transistors includes a gate structure extending lengthwise in a first direction; and
an interconnect structure disposed over the device layer,
wherein:
the interconnect structure includes a bottommost metal line layer electrically coupled to the transistors in the device layer,
the bottommost metal line layer includes metal lines arranged in first, second, third, fourth, fifth, and sixth metal tracks in order from first to sixth along the first direction,
a distance between any adjacent two of the first, second, third, fourth, fifth, and six metal tracks measured along the first direction is uniform,
the first metal track includes a metal line electrically coupled to an electric ground of the memory cell, and
the sixth metal track includes a metal line electrically coupled to a power supply of the memory cell.
2 . The memory cell of claim 1 , wherein the memory cell includes a write-port and a read-port, and the fifth metal track includes a metal line coupled to a read-port bit line of the memory cell.
3 . The memory cell of claim 2 , wherein the metal line of the fifth metal track extends entirely through a boundary of the memory cell in a second direction perpendicular to the first direction.
4 . The memory cell of claim 2 , wherein the metal line of the fifth metal track is configured as a landing pad coupled to the read-port bit line.
5 . The memory cell of claim 1 , wherein the metal line of the sixth metal track is configured as a landing pad coupled to the power supply.
6 . The memory cell of claim 5 , wherein the sixth metal track includes another metal line configured as a landing pad coupled to a read-port word line of the memory cell.
7 . The memory cell of claim 1 , wherein the memory cell includes a storage node and a complementary storage node, and the third metal track includes a metal line coupled to the storage node.
8 . The memory cell of claim 7 , wherein the fourth metal track includes a metal line coupled to the complementary storage node.
9 . The memory cell of claim 7 , wherein the fifth metal track includes a metal line coupled to the complementary storage node.
10 . The memory cell of claim 7 , wherein the metal line of the third metal track crosses over the gate structure of one of the transistors that has a gate contact coupled to the complementary storage node.
11 . An integrated circuit structure, comprising:
a device layer including a first gate structure of a first pass-gate transistor, a second gate structure shared by a first pull-down transistor and a first pull-up transistor, a third gate structure shared by a second pull-down transistor and a second pull-up transistor, and a fourth gate structure of a second pass-gate transistor, each of the gate structures extending lengthwise in a first direction; and
a metal layer suspended above the device layer, the metal layer including first, second, third, fourth, fifth, and sixth metal tracks arranged in order from first to sixth along the first direction and each extending lengthwise in a second direction perpendicular to the first direction,
wherein the third metal track includes a metal line crossing over the third gate structure, and one of the fourth metal track or the fifth metal track includes a metal line crossing over the second gate structure.
12 . The integrated circuit structure of claim 11 , wherein the fifth metal track includes the metal line crossing over the second gate structure, and the fourth metal track includes a metal island that is electrically floating.
13 . The integrated circuit structure of claim 11 , wherein the fourth metal track includes the metal line crossing over the second gate structure, the metal line of the fourth metal track electrically coupled to the third gate structure, and the metal line of the third metal track electrically coupled to the second gate structure.
14 . The integrated circuit structure of claim 11 , wherein the first and sixth metal tracks include metal lines coupled to a power supply and an electric ground of the device layer.
15 . The integrated circuit structure of claim 11 , wherein the device layer further includes a fifth gate structure of a third pass-gate transistor, the first and second pass-gate transistors are of a first conductivity type, and the third pass-gate transistor is of a second conductivity type opposite to the first conductivity type.
16 . The integrated circuit structure of claim 15 , wherein the sixth metal track includes a metal line coupled to the fifth gate structure.
17 . The integrated circuit structure of claim 15 , wherein the fourth metal track includes a metal line coupled to the fifth gate structure.
18 . A memory array, comprising:
a first memory cell having at least a first transistor;
a second memory cell having at least a second transistor, the second memory cell abutting the first memory cell, wherein the first and second transistors share a gate structure that extends across a boundary line between the first and second memory cells;
a gate contact disposed on the gate structure; and
a metal track suspended above the boundary line, wherein the metal track includes a first pad coupled to a power supply of the first and second memory cells and a second pad in physical contact with the gate contact.
19 . The memory array of claim 18 , wherein:
the first memory cell includes a write-port and a read-port,
the second memory cell includes a write-port and a read-port,
the first transistor is a pass-gate transistor of the read-port of the first memory cell, and
the second transistor is a pass-gate transistor of the read-port of the second memory cell.
20 . The memory array of claim 18 , wherein the metal track is a first metal track, the memory array further comprising:
a second metal track suspended above the first metal track, the second metal track including a third pad coupled to the first pad through a first via; and
a third metal track suspended above the second metal track, the third metal track including a power supply line coupled to the third pad through a second via.