Method for physically unclonable function through gate height tuning
A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).
1 . A method for physically unclonable function through gate height tuning, comprising:
providing a semiconductor substrate;
forming a high-k dielectric layer and a dummy silicon layer on said semiconductor substrate;
completely removing said dummy silicon layer, so that an original position of said dummy silicon layer is emptied to form recesses;
forming a work function layer and a metal filling layer on said high-k dielectric layer in said recesses;
performing a chemical mechanical planarization process to partially remove said metal filling layer and said work function layer, thereby remaining said metal filling layer and said work function layer form metal gates in said recesses and make heights of said metal gates lower than a critical gate height, wherein said critical gate height is set at a level higher than a bottom surface of said metal filling layer and depends on required gate work function; and
using said metal gates to manufacture programmed I/O pairs in an internal bias generator, wherein a local threshold voltage mismatching of said programmed I/O pairs becomes larger since said heights of said metal gates are lower than said critical gate height, so as to achieve random code generation in physically unclonable function.
2 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising outputting a bias voltage from said internal bias generator to one-time programmable memory, wherein increased said local threshold voltage mismatching of said programmed I/O pairs makes a distribution of said bias voltage outputted from said internal bias generator wider.
3 . The method for physically unclonable function through gate height tuning of claim 2 , further comprising reading said one-time programmable memory, wherein widened said distribution of said bias voltage outputted from said internal bias generator make a distribution of a read current read from said one-time programmable memory wider.
4 . The method for physically unclonable function through gate height tuning of claim 1 , wherein lengths of said metal gates are larger than lengths of surrounding normal gates, so that said heights of said metal gates are lower than heights of said normal gates after said chemical mechanical planarization process, so as to increase said local threshold voltage mismatching of said metal gates.
5 . The method for physically unclonable function through gate height tuning of claim 4 , wherein said metal gates are in a circuit area of physically unclonable function in a system-on-a-chip.
6 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising performing a thermal treatment after said chemical mechanical planarization process to change properties of remaining said work function layer of said metal gates, thereby modifying said local threshold voltage mismatching of said metal gates.
7 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising a silicon nitride layer formed on said dummy silicon layer, and further comprising performing another chemical mechanical planarization process before removing said dummy silicon layer to modify a thickness of said silicon nitride layer or completely remove said silicon nitride layer, thereby affecting said heights of finally-formed said metal gates.
8 . The method for physically unclonable function through gate height tuning of claim 1 , wherein said metal filling layer is not completely removed by said chemical mechanical planarization process, so as to change properties of remaining said work functions layer of said metal gates, thereby modifying said local threshold voltage of said metal gates.
9 . The method for physically unclonable function through gate height tuning of claim 1 , wherein said semiconductor substrate comprises an interface layer between said high-k dielectric layer and said semiconductor substrate on said interface layer.
10 . The method for physically unclonable function through gate height tuning of claim 1 , wherein said work function layer comprises a P-type work function layer and a N-type work function layer, a material of said P-type work function layer is titanium nitride (TiN), and a material of said N-type work function layer is titanium aluminide (TiAl).
11 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising a bottom barrier layer between said semiconductor substrate and said work function layer, and said bottom barrier layer is a multilayer structure formed of a tantalum nitride (TaN) layer and a titanium nitride layer.
12 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising a top barrier layer between said metal filling layer and said work function layer, and said top barrier layer is a multilayer structure formed of a titanium nitride layer and a titanium layer.
13 . The method for physically unclonable function through gate height tuning of claim 1 , further comprising a titanium aluminum oxide (TiAlO) capping layer on said metal filling layer and said work function layer.