Integrated circuits having replacement gate structures and methods for fabricating the same

1. A method of fabricating an integrated circuit comprising the steps of:

forming an interlayer dielectric (ILD) layer over a dummy gate stack, the dummy gate stack formed over a semiconductor substrate, the dummy gate stack comprising a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask;

removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer;

forming a thin liner along the ILD layer within the first opening;

extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack, thereby exposing a portion of the semiconductor substrate;

depositing at least one workfunction material layer within the first opening and within the first extended opening;

removing portions of the at least one workfunction material within the first opening; and depositing a low-resistance material over a remaining portion of the at least one workfunction material, thereby forming a replacement metal gate structure comprising the remaining portion of the at least one workfunction material and the low-resistance material.

2. The method of claim 1 , further comprising forming a capping layer over the replacement metal gate structure.

3. The method of claim 1 , wherein removing at least the upper portion of the dummy gate stack comprises removing the hardmask and removing a portion of the sidewall spacers.

4. The method of claim 1 , wherein forming the thin liner comprises conformally depositing the liner within the opening followed by removing the liner from remaining portions of the sidewall spacers and the dummy gate structure.

5. The method of claim 1 , wherein forming the thin liner comprises forming a thin silicon nitride liner.

6. The method of claim 1 , wherein depositing at least one workfunction material layer comprises depositing a workfunction metal layer that is thicker than half width of second opening.

7. The method of claim 6 , wherein depositing at least one workfunction material layer comprises depositing a first layer of the first workfunction material, a first layer of a second workfunction material over the first layer of the first layer of the first workfunction material, and a second layer of the first workfunction material over the first layer of the second workfunction material.

8. The method of claim 1 , further comprising depositing a barrier material layer prior to depositing the at least one workfunction material layer.

9. The method of claim 1 , further comprising removing the thin liner prior to depositing the at least one workfunction material layer.

10. The method of claim 1 , wherein removing portions of the at least one workfunction material comprises removing portions of the workfunction material that are adjacent to the ILD layer and that are above remaining portions of the sidewall spacers.

11. The method of claim 10 , further comprising depositing a sacrificial layer in the first opening prior to removing the portions of the workfunction material.

12. The method of claim 11 , further comprising removing the sacrificial layer subsequent to removing the portions of the workfunction material.

13. The method of claim 1 , further comprising re-forming at least of portion of the sidewall spacers subsequent to removing the portions of the at least one workfunction material.

14. The method of claim 1 , wherein depositing the at least one workfunction material comprises depositing a p-type workfunction material.

15. The method of claim 1 , wherein depositing the at least one workfunction material comprises depositing an n-type workfunction material.

16. A method of fabricating an integrated circuit comprising the steps of:

forming an interlayer dielectric (ILD) layer over a dummy gate stack, the dummy gate stack formed over a semiconductor substrate and a dummy oxide layer formed over the semiconductor substrate, the dummy gate stack comprising a dummy gate structure, a hardmask disposed over the dummy gate structure, and sidewall spacers disposed along sides of the dummy gate structure and the hardmask and over the dummy oxide layer;

removing at least an upper portion of the dummy gate stack to form a first opening within the ILD layer, wherein removing at least the upper portion comprises removing the hardmask and portions of the sidewall spacers adjacent to the hardmask;

forming a thin silicon nitride liner along the ILD layer within the first opening;

extending the first opening to form a first extended opening by completely removing the dummy gate structure of the dummy gate stack and a portion of the dummy oxide layer disposed thereunder, thereby exposing a portion of the semiconductor substrate;

depositing a layer of a first workfunction material and a layer of a second workfunction material within the first opening and within the first extended opening;

depositing an organic planarization layer within the first opening;

removing portions of the first and second workfunction material layers within the first opening, using the organic planarization layer as an etch mask;

removing the organic planarization layer;

re-forming a portion of the sidewall spacers;

depositing a low-resistance tungsten material over a remaining portion of the workfunction material layers and in between the re-formed portion of the sidewall spacers, thereby forming a replacement metal gate structure comprising the remaining portion of the workfunction material and the low-resistance material; and

forming a capping layer over the replacement metal gate structure.