Gate-top dielectric structure for self-aligned contact
Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present disclosure includes an active region having a channel region and a source/drain region, a gate structure over the channel region, a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure, an epitaxial source/drain feature over the source/drain region, a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer, a source/drain contact disposed over the epitaxial source/drain feature, and a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL. A sidewall of the source/drain contact is in direct contact with a sidewall of the CESL.
1 . A semiconductor structure, comprising:
an active region comprising a channel region and a source/drain region;
a gate structure over the channel region;
a gate spacer layer disposed over the channel region and extending along a sidewall of the gate structure;
an epitaxial source/drain feature over the source/drain region;
a contact etch stop layer (CESL) disposed on the epitaxial source/drain feature and extending along a sidewall of the gate spacer layer;
a source/drain contact disposed over the epitaxial source/drain feature; and
a dielectric cap layer disposed over the gate structure, the gate spacer layer and at least a portion of the CESL,
wherein a sidewall of the source/drain contact is in direct contact with a sidewall of the CESL,
wherein a top portion of the dielectric cap layer interfaces a sidewall of the source/drain contact.
2 . The semiconductor structure of claim 1 , wherein the active region comprises a fin structure and the gate structure wraps over the fin structure.
3 . The semiconductor structure of claim 1 , wherein the active region comprises a vertical stack of nanostructures and the gate structure wraps around each of nanostructures.
4 . The semiconductor structure of claim 1 , wherein top surfaces of the dielectric cap layer, the source/drain contact, and the CESL are coplanar.
5 . The semiconductor structure of claim 1 , wherein the dielectric cap layer comprises a dielectric constant between about 3.9 and about 10.
6 . The semiconductor structure of claim 1 , wherein the dielectric cap layer comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide,
aluminum oxide, zirconium silicate, or hafnium silicate.
7 . The semiconductor structure of claim 1 , wherein a dielectric constant of the dielectric cap layer is greater than a dielectric constant of the gate spacer layer.
8 . The semiconductor structure of claim 1 , wherein a dielectric constant of the dielectric cap layer is greater than a dielectric constant of the CESL.
9 . The semiconductor structure of claim 1 ,
wherein the active region extends lengthwise along a direction,
wherein the dielectric cap layer comprises a top width along the direction and a bottom width along the direction,
wherein the top width is greater than the bottom width.
10 . The semiconductor structure of claim 9 , wherein the dielectric cap layer comprises a curved sidewall such that a top portion of the sidewall is contact with the CESL and a bottom portion of the sidewall is contact with the gate spacer layer.
11 . A semiconductor structure, comprising:
a metal gate structure extending length width along a first direction;
a pair of gate spacer layers sandwiching the metal gate structure along a second direction perpendicular to the first direction;
a pair of contact etch stop layers sandwiching the pair of gate spacer layers along the second direction; and
a dielectric cap disposed over the metal gate structure, the pair of gate spacer layers, and at least a part of the pair of contact etch stop layers,
wherein the dielectric cap comprises a top width along the second direction and a bottom width along the second direction,
wherein the top width is greater than the bottom width,
wherein a portion of the dielectric cap extends into the metal gate structure.
12 . The semiconductor structure of claim 11 , wherein the dielectric cap comprises a curved sidewall such that a top portion of the curved sidewall is contact with the pair of contact etch stop layers and a bottom portion of the curved sidewall is contact with the pair of gate spacer layers.
13 . The semiconductor structure of claim 11 , wherein top surfaces of the metal gate structure and the dielectric cap are coplanar.
14 . The semiconductor structure of claim 11 , wherein the dielectric cap comprises a dielectric constant between about 3.9 and about 10.
15 . The semiconductor structure of claim 11 , wherein the dielectric cap comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, or hafnium silicate.
16 . The semiconductor structure of claim 11 , wherein the top width is greater than a distance between the pair of contact etch stop layers.
17 . A method, comprising:
forming a semiconductor element over a substrate, the semiconductor element including a channel region and a source/drain region;
forming a dummy gate stack over the channel region of the semiconductor element;
depositing a spacer layer over sidewalls of the dummy gate stack;
after the depositing of the spacer layer, etching the source/drain region of the semiconductor element to form a source/drain recess;
forming a source/drain feature in the source/drain recess;
depositing a contact etch stop layer (CESL) over sidewalls of the spacer layer and the source/drain feature;
depositing an interlayer dielectric (ILD) layer over the CESL;
performing a first planarization to expose the dummy gate stack;
replacing the dummy gate stack with a metal gate structure;
recessing the metal gate structure to form a recess;
depositing a dielectric layer over the recess;
performing a second planarization to expose the ILD layer;
anisotropically etching the source/drain feature, the CESL, the spacer layer, and the dielectric layer to form a contact opening;
depositing a metal layer over the contact opening to form a source/drain contact; and
performing a third planarization such that the source/drain contact, the CESL and the dielectric layer are coplanar.
18 . The method of claim 17 , wherein the dielectric layer comprises a dielectric constant between about 3.9 and about 10.
19 . The method of claim 17 , wherein the dielectric layer comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, or hafnium silicate.
20 . The method of claim 17 ,
wherein the recessing also recesses the spacer layer and the CESL,
wherein, after the third planarization, the dielectric layer comprises a curved sidewall such that a top portion of the curved sidewall is contact with the CESL and a bottom portion of the curved sidewall is contact with the spacer layer.