IP Library Granted Patent US 12,588,570
Granted Patent B2
US 12,588,570 · App. 18/828,516 · Granted Mar 24, 2026

Semiconductor device

Inventors: Hitoshi Imi (Yokohama Kanagawa, JP); Yutaka Horie (Mitaka Tokyo, JP); Shugo Suzuki (Hanno Saitama, JP); Yasutomo Sakurai (Kawasaki Kanagawa, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L25/162H01L23/49575H03K17/162H01L23/3107H01L24/48H01L2224/48245H02M1/08H10D1/68H10D30/47H10D30/60H10D62/8503
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,588,570
App. No.
18/828,516
Granted
Mar 24, 2026
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.

Claims (58)

1 . A semiconductor device comprising:

a first lead frame, a second lead frame, and a third lead frame;

a first transistor provided on the first lead frame and having a first terminal electrically connected to the first lead frame;

a second transistor provided on the second lead frame and having a first terminal electrically connected to the third lead frame;

a third transistor provided on the third lead frame and having a first terminal electrically connected to the third lead frame and a second terminal electrically connected to a second terminal of the first transistor;

a fourth transistor provided on the second lead frame and having a first terminal electrically connected to the second lead frame and a second terminal electrically connected to a second terminal of the second transistor;

a capacitor having a first terminal electrically connected to the first lead frame and a second terminal electrically connected to the second lead frame; and

a sealing resin configured to seal the first transistor, the second transistor, the third transistor, the fourth transistor, and the capacitor; wherein

the first transistor and the second transistor are GaN transistors, the third transistor and the fourth transistor are MOS transistors, and

the first transistor, the third transistor, the second transistor, and the fourth transistor are arranged side by side in this order in a first direction.

2 . The semiconductor device according to claim 1 , wherein

the first transistor and the second transistor are GaN-HEMTs.

3 . The semiconductor device according to claim 1 , wherein

the first transistor and the second transistor are normally-on transistors.

4 . The semiconductor device according to claim 1 , wherein

the third transistor and the fourth transistor are MOSFETS.

5 . The semiconductor device according to claim 1 , wherein

the third transistor and the fourth transistor are normally-off transistors.

6 . The semiconductor device according to claim 1 , wherein

the first lead frame and the first terminal of the first transistor are connected via a plurality of bonding wires,

the bonding wires include a first wire and a second wire extending in a direction different from a direction of the first wire, and

the second wire connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first wire.

7 . The semiconductor device according to claim 1 , further comprising

a control circuit configured to control driving of the first transistor, the second transistor, the third transistor, and the fourth transistor, wherein

the control circuit is sealed with the sealing resin.

8 . The semiconductor device according to claim 1 , further comprising

a fifth transistor provided on the second lead frame and having a first terminal electrically connected to the second lead frame, a second terminal electrically connected to the second terminal of the second transistor, and a gate terminal electrically connected to a gate terminal of the fourth transistor, wherein

the capacitor is provided side by side with the third transistor in a second direction intersecting the first direction, on the first lead frame and the second lead frame, and

the fifth transistor is provided side by side in the second direction on the capacitor side with the second transistor.

9 . The semiconductor device according to claim 8 , wherein

the fifth transistor is a MOSFET.

10 . The semiconductor device according to claim 8 , wherein

the fifth transistor is a normally-off transistor.

11 . The semiconductor device according to claim 8 , wherein

a threshold voltage of the fifth transistor is substantially the same as a threshold voltage of the fourth transistor.

12 . The semiconductor device according to claim 8 , wherein

the first lead frame and the first terminal of the first transistor are connected via a plurality of bonding wires,

the bonding wires include a first wire and a second wire extending in a direction different from a direction of the first wire, and

the second wire connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first wire.

13 . The semiconductor device according to claim 8 , further comprising

a control circuit configured to control driving of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor, wherein

the control circuit is sealed with the sealing resin.

14 . The semiconductor device according to claim 8 , further comprising

a sixth transistor provided on the third lead frame and having a first terminal electrically connected to the third lead frame, a second terminal electrically connected to the second terminal of the first transistor, and a gate terminal electrically connected to a gate terminal of the third transistor, wherein

the sixth transistor is provided so as to be sandwiched between the third transistor and the capacitor in the second direction.

15 . The semiconductor device according to claim 14 , wherein

the sixth transistor is a MOSFET.

16 . The semiconductor device according to claim 14 , wherein

the sixth transistor is a normally-off transistor.

17 . The semiconductor device according to claim 14 , wherein

a threshold voltage of the sixth transistor is substantially the same as a threshold voltage of the third transistor.

18 . The semiconductor device according to claim 14 , wherein

the first lead frame and the first terminal of the first transistor are connected via a plurality of bonding wires,

the bonding wires include a first wire and a second wire extending in a direction different from a direction of the first wire, and

the second wire connects the first terminal of the first transistor and the first terminal of the capacitor with a shorter distance than the first wire.

19 . The semiconductor device according to claim 14 , further comprising

a control circuit configured to control driving of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, wherein

the control circuit is sealed with the sealing resin.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2024
From: IMI, HITOSHI; HORIE, YUTAKA; SUZUKI, SHUGO; SAKURAI, YASUTOMO
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 068575/0001 →
Priority Claims (1)
JP 2024-082659 · May 21, 2024 · national
Continuity (1)
Related Publication 20250364509A1 · Nov 27, 2025
References Cited (10)
US 11303209B2 · Ikeda · 2022 [cited by examiner]
US 11367715B2 · Tonedachi · 2022 [cited by examiner]
US 11749578B2 · Takahashi · 2023 [cited by examiner]
JP 2020167748 · 2020 [cited by applicant]
JP 2020167869 · 2020 [cited by applicant]
JP 2021089971 · 2021 [cited by applicant]
JP 2022115706 · 2022 [cited by applicant]
JP 2023032303 · 2023 [cited by applicant]
WO WO2019065173 · 2020 [cited by applicant]
WO WO2020170650 · 2021 [cited by applicant]