Granted Patent B2

US 12,591,432 · App. 18/713,160 · Granted Mar 31, 2026

Inventors: Zhiping Zhang (Guangdong, CN); Zhijun Li (Guangdong, CN)

Assignee: BEIJING ZITIAO NETWORK TECHNOLOGY CO., LTD.

G06F9/3004G06F9/30189G06F9/321

Abstract

Claims (45)

1 . A method for execution of a bus controller, wherein the bus controller is connected to a target device by means of a target bus, the bus controller comprises an instruction memory, the instruction memory is used to store at least one instruction, the instruction corresponds to one or more bus sub-operations, and wherein the method comprises:

in response to receiving an instruction execution command, acquiring a target instruction of the at least one instruction from the instruction memory;

parsing the target instruction and then executing one or more corresponding bus sub-operations;

executing a corresponding control or data operation on the target device by means of the one or more bus sub-operations,

wherein, the bus sub-operation comprises sending reset timing, sending operation start timing, sending an operation command, sending a read and write flag bit operation, sending an address operation, sending a data operation, sending operation end timing, receiving a response bit operation, and receiving a data operation.

2 . The method for the execution according to claim 1 , wherein the bus controller is connected to a host through a local bus.

3 . The method for the execution according to claim 1 , wherein in response to receiving an instruction execution command, acquiring a target instruction of the at least one instruction from the instruction memory comprises:

in response to receiving an instruction execution command, reading instructions in the instruction memory in sequence; wherein, each instruction in the instruction memory comprises an instruction identification code, the instruction identification code is used to identify the instruction in the instruction memory.

4 . The method for the execution according to claim 1 , wherein the target instruction comprises an operand index, the method comprises:

identifying the operand index in the target instruction in response to acquiring the target instruction;

calling an instruction operand register which corresponds to the operand index.

5 . The method for the execution according to claim 1 , wherein the target instruction comprises a jump enable flag, the method comprises:

identifying the jump enable flag in the target instruction in response to acquiring the instruction;

performing a jump operation which corresponds to the jump enable flag.

6 . The method for the execution according to claim 1 , wherein the method comprises:

identifying an operand in the target instruction in response to acquiring the target instruction;

transmitting the operand to a data path controller.

7 . The method for the execution according to claim 4 , wherein the method comprises:

identifying a jump value in the target instruction in response to acquiring the instruction;

jumping to a specified instruction memory address according to the jump value.

8 . The method for the execution according to claim 1 , wherein the target instruction further comprises a reserved field, the reserved field is used to extend the target instruction.

9 . The method for the execution according to claim 1 , wherein the method further comprises:

writing the target instruction corresponding to the bus sub-operation into the instruction memory.

10 . The method for the execution according to claim 1 , wherein the method further comprises:

setting a program start address register, initializing a program counter, and executing the bus sub-operation corresponding to the target instruction starting from a specified instruction memory address.

11 . The method for the execution according to claim 1 , wherein the method further comprises:

setting a program execution number register, and controlling a number of executions of the target instruction in the instruction memory.

12 . The method for the execution according to claim 1 , wherein the method comprises:

setting a program counter in an instruction execution controller;

connecting an output of the program counter to a read address port of the instruction memory, and reading the instruction stored in an instruction memory address.

13 . A computer device, comprising a memory and a processor, the memory storing a computer program, wherein the processor implements blocks of a method for execution of a bus controller in response to executing the computer program, the bus controller is connected to a target device by means of a target bus, the bus controller comprises an instruction memory, the instruction memory is used to store at least one instruction, the instruction corresponds to one or more bus sub-operations, and wherein the method comprises:

in response to receiving an instruction execution command, acquiring a target instruction of the at least one instruction from the instruction memory;

parsing the target instruction and then executing one or more corresponding bus sub-operations;

executing a corresponding control or data operation on the target device by means of the one or more bus sub-operations,

wherein, the bus sub-operation comprises sending reset timing, sending operation start timing, sending an operation command, sending a read and write flag bit operation, sending an address operation, sending a data operation, sending operation end timing, receiving a response bit operation, and receiving a data operation.

14 . A non-transitory computer-readable storage medium, storing a computer program, wherein the computer program implements blocks of a method for execution of a bus controller in response to being executed by a processor, the bus controller is connected to a target device by means of a target bus, the bus controller comprises an instruction memory, the instruction memory is used to store at least one instruction, the instruction corresponds to one or more bus sub-operations, and wherein the method comprises:

in response to receiving an instruction execution command, acquiring a target instruction of the at least one instruction from the instruction memory;

parsing the target instruction and then executing one or more corresponding bus sub-operations;

executing a corresponding control or data operation on the target device by means of the one or more bus sub-operations,

wherein, the bus sub-operation comprises sending reset timing, sending operation start timing, sending an operation command, sending a read and write flag bit operation, sending an address operation, sending a data operation, sending operation end timing, receiving a response bit operation, and receiving a data operation.

15 . A method for execution of a bus controller, wherein the bus controller is connected to a target device by means of a target bus, the bus controller comprises an instruction memory, the instruction memory is used to store at least one instruction, the instruction corresponds to one or more bus sub-operations, and wherein the method comprises:

in response to receiving an instruction execution command, acquiring a target instruction of the at least one instruction from the instruction memory;

parsing the target instruction and then executing one or more corresponding bus sub-operations;

executing a corresponding control or data operation on the target device by means of the one or more bus sub-operations,

wherein the bus controller comprises registers, the registers comprise a control register, a status register, a bus configuration register, an instruction operand register, a storage control register, and an interruption register.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (23)