Distributed write driver for memory array
The disclosed technology relates to a write driver and a method for operating the write driver for a memory device. The write driver is connected to a memory line of the memory device. Multiple memory cells of the memory device are connected to the memory line at different distances from the write driver. The operating method comprises controlling the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells, and controlling the write driver to provide a larger amount of current for accessing a second memory cell of the memory cells. Thereby, the first memory cell is connected to the memory line at a smaller distance to the write driver than the second memory cell.
1 . A method of operating a write driver for a memory device, the method comprising:
providing the memory device comprising the write driver connected to a memory line of the memory device, wherein multiple memory cells of the memory device are connected to the memory line at different distances from the write driver, and wherein the write driver comprises a plurality of transistors;
controlling the write driver to activate a first set of the transistors for accessing a first memory cell of the memory cells;
controlling the write driver to activate a second set of the transistors for accessing a second memory cell of the memory cells;
controlling the write driver to provide a smaller amount of current for accessing the first memory cell; and
controlling the write driver to provide a larger amount of current for accessing the second memory cell;
wherein the first memory cell is connected to the memory line at a smaller distance to the write driver along the memory line than the second memory cell, and
wherein:
the first set of the transistors includes fewer transistors than the second set of the transistors, or the plurality of transistors have different transistor widths and a sum of widths of one or more transistors included in the first set of the transistors is smaller than a sum of widths of one or more transistors included in the second set of the transistors.
2 . The method according to claim 1 , wherein each transistor width of the plurality of transistors is an integer multiple of a base transistor width.
3 . The method according to claim 1 , wherein the first memory cell is included in a first set of the memory cells and the second memory cell is included in a second set of the memory cells, and wherein the method further comprises:
controlling the write driver to activate the first set of the transistors for accessing a memory cell of the first set of the memory cells; and
controlling the write driver to activate the second set of the transistors for accessing a memory cell of the second set of the memory cells.
4 . The method according to claim 1 , wherein the method further comprises:
controlling the write driver to provide a shorter voltage pulse to the memory line for accessing the first memory cell; and
controlling the write driver to provide a longer voltage pulse to the memory line for accessing the second memory cell.
5 . The method according to claim 4 , wherein the first memory cell is included in a first set of the memory cells and the second memory cell is included in a second set of the memory cells, and wherein the method further comprises:
controlling the write driver to provide a shorter voltage pulse to the memory line for accessing a memory cell of the first set of the memory cells; and
controlling the write driver to provide a longer voltage pulse longer than the shorter voltage pulse to the memory line for accessing a memory cell of the second set of the memory cells.
6 . The method according to claim 5 , wherein a pulse width of the shorter voltage pulse or the longer voltage pulse provided to the memory line is controlled using a configurable delay.
7 . The method according to claim 1 , wherein:
the memory line is a bit line of the memory device, and accessing the first memory cell or the second memory cell comprises writing into the first memory cell or the second memory cell, respectively.
8 . The method according to claim 1 , wherein:
the memory line is a word line of the memory device, and accessing the first memory cell or the second memory cell comprises activating the first memory cell or the second memory cell, respectively.
9 . The method according to claim 1 , wherein the memory cells of the memory device comprise voltage-controlled magnetic anisotropy memory cells, phase change memory cells, spin-orbit torques memory cells, or spin-transfer torque memory cells.
10 . A write driver for a memory device,
wherein the write driver is connectable to an end of a memory line of the memory device, wherein multiple memory cells of the memory device are connected to the memory line at different distances from the end of the memory line, and wherein the write driver comprises a plurality of transistors and a controller configured to:
control the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells;
control the write driver to provide a larger amount of current larger than the smaller amount for accessing a second memory cell of the memory cells,
wherein the first memory cell is connected to the memory line at a smaller distance to the end of the memory line along the memory line than the second memory cell, and
control each one of the plurality of transistors with an individual control signal.
11 . The write driver according to claim 10 , wherein the plurality of the transistors comprises one or more transistors having a first transistor width and one or more transistors having a second transistor width.
12 . The write driver according to claim 10 , wherein the controller is configured to:
control the write driver to output a shorter voltage pulse, which results in a shorter current duration, for providing the smaller amount of current; and
control the write driver to output a longer voltage pulse, which results in a longer current duration, for providing the larger amount of current.
13 . A memory device comprising:
a plurality of bit lines and a plurality of word lines;
a plurality of write drivers each connected to an end of one of the bit lines or an end of one of the word lines; and
a plurality of memory cells, wherein each of the bit lines and the word lines has connected thereto multiple ones of the memory cells at different distances from the end of the each of the bit lines and the word lines,
wherein each of the write drivers comprises a plurality of transistors and a controller configured to control each one of the transistors with an individual control signal,
wherein each of the write drivers is configured to provide different a smaller amount of current for accessing a first memory cell of the memory cells and to provide a larger amount of current larger than the smaller amount for accessing a second memory cell of the memory cells, and
wherein the first memory cell is connected to the memory line at a smaller distance to the end of the memory line along the memory line than the second memory cell.
14 . The memory device according to claim 13 , wherein the plurality of transistors comprises one or more transistors having a first transistor width and one or more transistors having a second transistor width.
15 . The memory device according to claim 13 , wherein the controller is configured to:
control the write driver to output a shorter voltage pulse, which results in a shorter current duration, for providing the smaller amount of current; and
control the write driver to output a longer voltage pulse, which results in a longer current duration, for providing the larger amount of current.
16 . The memory device according to claim 13 , wherein the memory cells comprise voltage-controlled magnetic anisotropy memory cells, phase change memory cells, spin-orbit torques memory cells, or spin-transfer torque memory cells.