Self-aligned backside contact with increased contact area
A first source drain region adjacent to a first transistor, a second source drain region adjacent to a second transistor, an upper source drain contact above the first source drain region, a bottom source drain contact below the second source drain region, the bottom and the upper source drain contacts are on opposite sides, a horizontal surface of the bottom source drain contact is adjacent to a horizontal surface of dielectric side spacers surrounding the second source drain region. An embodiment where a bottom source drain contact surrounds vertical sides of a source drain region. A method including forming a first and a second nanosheet stacks, forming a top source drain contact to a first source drain region adjacent to the first nanosheet stack, forming a bottom source drain contact to a lower horizontal surface of a second source drain region adjacent to the second nanosheet stack.
1 . A semiconductor device comprising:
a first source drain;
a frontside contact structure below and directly contacting the first source drain;
a second source drain, wherein both the first source drain and the second source drain are in a same horizontal plane;
first sidewall spacers arranged on opposite sidewalls of the second source drain; and
a backside contact structure above and directly contacting the second source drain,
wherein inner sidewalls of the backside contact structure directly contact the opposite sidewalls of the second source drain, and
wherein top surfaces of the first sidewall spacers directly contact bottommost surfaces of the backside contact structure.
2 . The semiconductor device according to claim 1 , wherein a width of the backside contact structure is greater than a width of the second source drain measured in a horizontal direction perpendicular to a gate length.
3 . The semiconductor device according to claim 1 , wherein the bottommost surfaces of the backside contact structure are below a topmost surface of the second source drain.
4 . The semiconductor device according to claim 1 , wherein a width of a first portion of the backside contact structure measured from one sidewall of the inner sidewalls in a horizontal direction perpendicular to a gate length is equal to a width of one sidewall spacer of the first sidewall spacers measured from the one sidewall of the inner sidewalls in the horizontal direction perpendicular to the gate length.
5 . The semiconductor device according to claim 1 , further comprising:
a bottom dielectric isolation layer between and physically separating the backside contact structure from a gate structure, wherein a top surface of the first source drain is substantially flush with a topmost surface of the bottom dielectric isolation layer, and wherein a top surface of the second source drain is below the topmost surface of the bottom dielectric isolation layer.
6 . The semiconductor device according to claim 1 , further comprising:
second sidewall spacers arranged on opposite sidewalls of the first source drain, wherein bottommost surfaces of the second sidewall spacers are substantially flush with bottommost surfaces of the first sidewall spacers, wherein a height of the first sidewall spacers is less than a height of the second sidewall spacers.
7 . The semiconductor device according to claim 1 , further comprising:
a bottom dielectric isolation layer between and physically separating the backside contact structure from a gate structure, wherein the first sidewall spacers and the bottom dielectric isolation layer are made from a same material, and wherein the backside contact structure directly contacts both a top and a side of the bottom dielectric isolation layer.
8 . A semiconductor device comprising:
a frontside contact structure directly below and electrically connected to a first source drain;
a backside contact structure directly above and electrically connected to a second source drain, wherein both the first source drain and the second source drain are in a same horizontal plane; and
first sidewall spacers arranged on opposite sidewalls of the second source drain;
wherein a topmost surface of the second source drain is below a topmost surface of the first source drain.
9 . The semiconductor device according to claim 8 , wherein a width of the backside contact structure is greater than a width of the second source drain measured in a a horizontal direction perpendicular to a gate length.
10 . The semiconductor device according to claim 8 , wherein bottommost surfaces of the backside contact structure are below the topmost surface of the second source drain.
11 . The semiconductor device according to claim 8 , wherein a width of a first portion of the backside contact structure measured in a horizontal direction perpendicular to a gate length is equal to a width of one sidewall spacer of the first sidewall spacers measured in the horizontal direction perpendicular to the gate length.
12 . The semiconductor device according to claim 8 , wherein top surfaces of the first sidewall spacers directly contact bottom surfaces of the backside contact structure.
13 . The semiconductor device according to claim 8 , further comprising:
second sidewall spacers arranged on opposite sidewalls of the first source drain, wherein bottommost surfaces of the second sidewall spacers are substantially flush with bottommost surfaces of the first sidewall spacers, wherein a height of the first sidewall spacers is less than a height of the second sidewall spacers.
14 . The semiconductor device according to claim 8 , further comprising:
a bottom dielectric isolation layer between and physically separating the backside contact structure from a gate structure, wherein the first sidewall spacers and the bottom dielectric isolation layer are made from a same material, and wherein the backside contact structure directly contacts both a top and a side of the bottom dielectric isolation layer.
15 . A semiconductor device comprising:
a source drain;
sidewall spacers arranged on opposite sidewalls of the source drain; and
a backside contact structure above and directly contacting the source drain,
wherein inner sidewalls of the backside contact structure directly contact the opposite sidewalls of the source drain, and
wherein top surfaces of the sidewall spacers directly contact bottommost surfaces of the backside contact structure.
16 . The semiconductor device according to claim 15 , wherein a width of the backside contact structure is greater than a width of the source drain measured in a a horizontal direction perpendicular to a gate length.
17 . The semiconductor device according to claim 15 , wherein the bottommost surfaces of the backside contact structure are below a topmost surface of the source drain.
18 . The semiconductor device according to claim 15 , wherein a width of a first portion of the backside contact structure measured from one sidewall of the inner sidewalls in a horizontal direction perpendicular to a gate length is equal to a width of one sidewall spacer of the sidewall spacers measured from the one sidewall of the inner sidewalls in the horizontal direction perpendicular to the gate length.
19 . The semiconductor device according to claim 15 , further comprising:
a bottom dielectric isolation layer between and physically separating the backside contact structure from a gate structure, wherein a top of the source drain is below a topmost surface of the bottom dielectric isolation layer and above a bottommost surface of the bottom dielectric isolation layer.
20 . The semiconductor device according to claim 15 , further comprising:
a bottom dielectric isolation layer between and physically separating the backside contact structure from a gate structure, wherein the sidewall spacers and the bottom dielectric isolation layer are made from a same material, and wherein the backside contact structure directly contacts both a top and a side of the bottom dielectric isolation layer.