IP Library Granted Patent US 12,596,500
Granted Patent B2
US 12,596,500 · App. 18/227,216 · Granted Apr 7, 2026

Bloom filter integration into a controller

Inventors: Edmund J. Gieske (Cedar Park, TX); Cagdas Dirik (Indianola, WA); Elliott C. Cooper-Balis (San Jose, CA); Robert M. Walker (Raleigh, NC); Amitava Majumdar (Boise, ID); Sujeet Ayyapureddi (Boise, ID); Yang Lu (Boise, ID); Ameen D. Akel (Rancho Cordova, CA); Niccolò Izzo (Vignate, IT); Danilo Caraccio (Milan, IT); Markus H. Geiger (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0656G06F3/0604G06F3/0673G06F12/0802G06F2212/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,596,500
App. No.
18/227,216
Granted
Apr 7, 2026
Kind
B2
Abstract

Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

Claims (44)

1 . An apparatus, comprising:

a memory device having a refresh interval comprising a maximum time interval between refresh operations of the memory device; and

a memory controller coupled to the memory device, the memory controller configured to:

detect whether an activate command is in a portion of the memory device that is being monitored by a counting bloom filter, wherein the counting bloom filter is integrated into the memory controller;

increment the counting bloom filter in response to the activate command being detected in the portion of the memory device that is being monitored by the counting bloom filter;

determine whether a value of the counting bloom filter exceeds a threshold value for row hammer detection, wherein the memory controller is configured to skip the determination of whether the value of the counting bloom filter exceeds the threshold value for row hammer detection for an initial refresh interval and determine whether the value of the counting bloom filter exceeds the threshold value for row hammer detection during a second refresh interval; and

perform row hammer mitigation in response to the value exceeding the threshold value for row hammer detection.

2 . The apparatus of claim 1 , wherein the memory device includes a plurality of banks or channels; and

wherein the counting bloom filter includes a plurality of tables corresponding to the plurality of banks or channels.

3 . The apparatus of claim 2 , wherein the memory controller is configured to increment the counting bloom filter in response to each row activate command received by the memory device within a time period;

wherein the memory controller includes a single-port memory configured to provide storage for the plurality of tables; and

wherein a capacity of the single-port memory corresponds to a quantity of rows that can be activated within the time period.

4 . The apparatus of claim 3 , wherein the time period is a refresh interval of the memory device.

5 . The apparatus of claim 1 , wherein the memory device includes a plurality of banks or channels; and

wherein the memory controller is configured to increment a respective counting bloom filter in response to a row activate command received by the memory device for a corresponding bank or channel within a time period.

6 . The apparatus of claim 5 , wherein the memory controller includes a respective single-port memory configured to provide storage for the respective counting bloom filter; and

wherein a capacity of the single-port memory corresponds to a quantity of rows that can be activated in the corresponding bank or channel within the time period.

7 . The apparatus of claim 5 , wherein the memory controller is configured to maintain a quantity of counting bloom filters equal to a quantity of the plurality of banks or channels.

8 . The apparatus of claim 1 , wherein the memory controller is configured to increment the counting bloom filter in response to a cache miss.

9 . An apparatus, comprising:

a memory device having a refresh interval comprising a maximum time interval between refresh operations of the memory device; and

a memory controller coupled to the memory device, the memory controller including a first counting bloom filter and a second counting bloom filter, wherein the memory controller is configured to:

detect whether an activate command is in a portion of the memory device that is being monitored by the first counting bloom filter and the second counting bloom filter, wherein the first counting bloom filter and the second counting bloom filter are integrated into the memory controller;

increment the first counting bloom filter and the second counting bloom filter in response to a portion of the memory device that is being monitored by the first counting bloom filter and the second counting bloom filter receiving a row activate command;

determine whether a first value of the first counting bloom filter or a second value of the second counting bloom filter exceeds a threshold value for row hammer detection on alternating refresh intervals, out of phase with each other, wherein the memory controller is configured to skip the determination of whether the first value of the first counting bloom filter or the second value of the second counting bloom filter exceeds the threshold value for row hammer detection for an initial refresh interval and determine whether the first value of the first counting bloom filter or the second value of the second counting bloom filter exceeds the threshold value for row hammer detection during a second refresh interval; and

perform row hammer mitigation in response to the first value or the second value exceeding the threshold value for row hammer detection.

10 . The apparatus of claim 9 , wherein the first counting bloom filter and the second counting bloom filter have a same structure; and

wherein the memory controller is configured to refresh the first counting bloom filter and the second counting bloom filter on alternating refresh intervals, out of phase with each other.

11 . The apparatus of claim 9 , wherein the memory controller is configured to increment the first counting bloom filter and the second counting bloom filter in response to a cache miss.

12 . A method, comprising:

detecting whether a row activate command is in a portion of a memory device that is being monitored by a counting bloom filter, wherein the counting bloom filter is integrated into a memory controller and the memory device has a refresh interval comprising a maximum time interval between refresh operations of the memory device;

in response to the row activate command being detected in the portion of the memory device that is being monitored by the counting bloom filter, incrementing a corresponding value of the counting bloom;

determining whether the corresponding value of the counting bloom filter exceeds a threshold value of row hammer detection, wherein the memory controller is configured to skip the determination of whether the value of the counting bloom filter exceeds the threshold value of row hammer detection for an initial refresh interval and determine whether the corresponding value of the counting bloom filter exceeds the threshold value for row hammer detection during a second refresh interval; and

executing, by the memory controller, row hammer mitigation in response to the corresponding value exceeding the threshold value of row hammer detection.

13 . The method of claim 12 , further comprising, in response to the row activate command of the memory device being detected:

hashing an address associated with the row activate command to produce a resulting value; and

wherein incrementing the corresponding value comprises incrementing a value of the counting bloom filter corresponding to the resulting value.

14 . The method of claim 12 , further comprising decrementing the corresponding value of the counting bloom filter after at least one other row activate command of the memory device is detected.

15 . The method of claim 12 , further comprising dealiasing the counting bloom filter.

16 . The method of claim 15 , wherein incrementing the corresponding value of the counting bloom filter comprises incrementing a plurality of corresponding values of the counting bloom filter; and

wherein dealiasing comprises determining whether a minimum value of the plurality of corresponding values of the counting bloom filter exceeds the threshold value for row hammer detection.

17 . The method of claim 15 , wherein dealiasing includes adding a row identification (ID) tag and a unique flag to a counter.

18 . The method of claim 15 , wherein dealiasing includes adding a dealiasing table when an additional counting bloom filter is added to the memory controller.

19 . The method of claim 12 , further comprising detecting and correcting, by the memory controller, errors in data output by the counting bloom filter in parallel to the counting bloom filter incrementing counters.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: GIESKE, EDMUND J.; DIRIK, CAGDAS; COOPER-BALIS, ELLIOTT C.; WALKER, ROBERT M.; MAJUMDAR, AMITAVA; AYYAPUREDDI, SUJEET; LU, YANG; AKEL, AMEEN D.; IZZO, NICCOLÒ; CARACCIO, DANILO; GEIGER, MARKUS H.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 064410/0292 →
Continuity (2)
Provisional Application 63392835 · Jul 27, 2022
Related Publication 20240036762A1 · Feb 1, 2024
References Cited (11)
US 11347808B1 · Plenderleith · 2022 [cited by examiner]
US 20140029367A1 · Jung · 2014 [cited by examiner]
US 20140189215A1 · Kang · 2014 [cited by examiner]
US 20190073161A1 · Nale · 2019 [cited by examiner]
US 20190213218A1 · Sharifi Tehrani · 2019 [cited by examiner]
US 20200034305A1 · Agarwala · 2020 [cited by examiner]
US 20200342934A1 · Lee · 2020 [cited by examiner]
US 20210390998A1 · Delcheh · 2021 [cited by applicant]
H. Song, F. Hao, M. Kodialam and T. V. Lakshman, “IPV6 Lookups using Distributed and Load Balanced Bloom Filters for 100Gbps Core Router Line Cards,” IEEE INFOCOM 2009, Rio de Janeiro, Brazil, 2009, pp. 2518-2526, doi: … [cited by examiner]
M. J. Kim et al., “Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh,” 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea, Republic of,… [cited by examiner]
A. G. Yaǧlikçi et al., “BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows,” 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea (South)… [cited by applicant]