Semiconductor device and electronic system including the same
A semiconductor device and an electronic system including the same are disclosed. The semiconductor device may include a substrate including a cell array region and a connection region, the cell array region comprising a center region and an outer region; an electrode structure including electrodes and pads; vertical structures on the cell array region and penetrating the electrode structure; and a separation insulating pattern penetrating and dividing an upper electrode, which is one of the electrodes, into at least two portions arranged in a second direction crossing the first direction. The separation insulating pattern comprises a first portion and a second portion, the first portion is between at least some of the central vertical structures, and the second portion is spaced apart from the first portion such that, when viewed in the plan view, the second portion is between at least some of the peripheral vertical structure.
1 . A semiconductor device, comprising:
a substrate including a cell array region and a connection region arranged along a first direction, the cell array region comprising a center region and an outer region arranged along the first direction, the outer region of the cell array region disposed between the center region of the cell array region and the connection region along the first direction;
an electrode structure including a plurality of electrodes and a plurality of pads, the plurality of electrodes vertically stacked on the substrate and spaced apart from each other in a vertical direction perpendicular to the first direction, the plurality of pads disposed over the connection region;
a plurality of vertical structures in the cell array region extending through the electrode structure in the vertical direction, the plurality of vertical structures comprising:
a plurality of central vertical structures disposed in the center region of the cell array region, and
a plurality of peripheral vertical structures disposed in the outer region of the cell array region;
a plurality of vertical supporting structures in the connection region extending through the plurality of pads; and
a separation insulating pattern extending through an upper electrode of the plurality of electrodes, the separation insulating pattern dividing the upper electrode into at least two portions in a second direction perpendicular to the first direction and the vertical direction, wherein the at least two portions are electrically isolated from each other,
wherein the plurality of central vertical structures comprises a first vertical structure, which overlaps with the separation insulating pattern,
the plurality of peripheral vertical structures comprises a second vertical structure, which overlaps with the separation insulating pattern, and
when viewed on a plane perpendicular to the vertical direction, an overlapping area between the first vertical structure and the separation insulating pattern is larger than an overlapping area between the second vertical structure and the separation insulating pattern, and
wherein, when viewed on the plane perpendicular to the vertical direction, a center of the second vertical structure of the plurality of peripheral vertical structures is spaced apart from the separation insulating pattern.
2 . The semiconductor device of claim 1 , further comprising:
bit lines on the cell array region and extended in a second direction which crosses the first direction, and
wherein the plurality of peripheral vertical structures are electrically isolated from the bit lines.
3 . The semiconductor device of claim 1 , wherein the first vertical structure and the second vertical structure have a same width in the first direction.
4 . The semiconductor device of claim 1 , further comprising:
an electrode barrier layer between the separation insulating pattern and the upper electrode.
5 . The semiconductor device of claim 1 ,
wherein a vertical supporting structure of the plurality of vertical supporting structures has a width larger than a width of a vertical structure of the plurality of vertical structures.
6 . The semiconductor device of claim 1 , wherein a top surface of the separation insulating pattern is at a same vertical level as top surfaces of the plurality of vertical structures.
7 . An electronic system, comprising:
a main substrate;
a semiconductor device on the main substrate; and
a controller on the main substrate and electrically connected to the semiconductor device,
wherein the semiconductor device comprises:
a substrate including a cell array region and a connection region arranged along a first direction, the cell array region comprising a center region and an outer region arranged along the first direction, the outer region of the cell array region disposed between the center region of the cell array region and the connection region along the first direction,
an electrode structure including a plurality of electrodes and a plurality of pads, the plurality of electrodes vertically stacked on the substrate and spaced apart from each other in a vertical direction perpendicular to the first direction, the plurality of pads disposed over the connection region,
a plurality of vertical structures in the cell array region extending through the electrode structure in the vertical direction, the plurality of vertical structures comprising:
a plurality of central vertical structures disposed in the center region of the cell array region, and
a plurality of peripheral vertical structures disposed in the outer region of the cell array region, and
a separation insulating pattern extending through an upper electrode of the plurality of electrodes, the separation insulating pattern dividing the upper electrode into at least two portions arranged in a second direction perpendicular to the first direction and the vertical direction,
wherein the plurality of central vertical structures comprises a first vertical structure, which overlaps with the separation insulating pattern,
the plurality of peripheral vertical structures comprises a second vertical structure, which overlaps with the separation insulating pattern,
when viewed on a plane perpendicular to the vertical direction, an overlapping area between the first vertical structure and the separation insulating pattern is larger than an overlapping area between the second vertical structure and the separation insulating pattern, and
wherein, when viewed on the plane perpendicular to the vertical direction, a center of the second vertical structure of the plurality of peripheral vertical structures is spaced apart from the separation insulating pattern.
8 . The electronic system of claim 7 , further comprising:
bit lines on the cell array region and extending in the second direction, and
wherein the plurality of peripheral vertical structures are electrically isolated from the bit lines.