Controller memory buffer (CMB) as cache
A controller memory buffer (CMB) is used by a host device for numerous purposes. One such purpose is to have data placed in CMB in response to a read command. The data is read from the memory device and placed in the CMB. However, for efficiency purposes, the data storage device may pre-fetch data. Pre-fetched data is stored in volatile memory that is distinct from CMB, but oftentimes in dynamic random access memory (DRAM), of which the CMB is a part. Rather than copying the data from DRAM and restoring the data in CMB, the data storage device can simply provide the DRAM address without moving the data to CMB, thus saving the step of copying data from DRAM to CMB.
1 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a read command from a host device, wherein the read command has a logical block address (LBA), and wherein the read command is to read data for the LBA from the memory device to a location in a controller memory buffer (CMB);
forward the LBA to a LBA to dynamic random access memory (DRAM) (L2D) module;
scan a list in the L2D module;
determine whether the LBA matches an entry in the list;
pre-fetch data for at least one LBA from the memory device and store the pre-fetched data in DRAM at a DRAM address;
inform the L2D module of the LBA and the DRAM address; and
receive a Physical region page (PRP) with the read command and send the PRP to the L2D module.
2 . The data storage device of claim 1 , wherein the controller is configured to:
return the LBA to a CMB manager upon determining that the LBA does not match an entry in the list; and
read the data from the memory device.
3 . The data storage device of claim 1 , wherein the controller is configured to determine that the LBA matches an entry on the list, and wherein the L2D module is configured to return a new address to a CMB manager.
4 . The data storage device of claim 3 , wherein the new address corresponds to a location in DRAM.
5 . The data storage device of claim 4 , wherein the CMB is disposed in the DRAM, and wherein the new address is not in the CMB.
6 . The data storage device of claim 1 , wherein the list contains addresses pre-fetched by the controller from the memory device.
7 . The data storage device of claim 1 , wherein the L2D contains LBA to PRP information and LBA to DRAM address information.
8 . The data storage device of claim 1 , wherein the controller is configured to dynamically remap the PRP to the DRAM address.
9 . The data storage device of claim 1 , wherein the L2D module is configured to maintain a list of LBA to physical region page (PRP) relationships and LBA to DRAM addresses.
10 . A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
pre-fetch data from the memory device prior to receiving a read command to read the data from the memory device, wherein the pre-fetched data has a logical block address (LBA);
store the pre-fetched data in dynamic random access memory (DRAM) at a DRAM address;
inform a LBA to DRAM (L2D) module of the LBA for the pre-fetched data and the DRAM address;
receive the read command, wherein the read command is to read the data from the memory device to a controller memory buffer (CMB);
access the data from the DRAM:
receive a physical region page (PRP) for the read command; and
send the PRP to the L2D module.
11 . The data storage device of claim 10 , wherein the controller is configured to search a table in the L2D module for a match for the LBA.
12 . The data storage device of claim 10 , wherein the controller is configured to dynamically remap the PRP to the DRAM address.
13 . The data storage device of claim 10 , wherein the controller is configured to not copy the data from the DRAM to the CMB upon receipt of the read command.
14 . The data storage device of claim 10 , wherein the L2D module is configured to maintain a list of LBA to physical region page (PRP) relationships and LBA to DRAM addresses.
15 . The data storage device of claim 10 , wherein the CMB is disposed in the DRAM.
16 . The data storage device of claim 10 , wherein the L2D contains LBA to PRP information and LBA to DRAM address information.
17 . A data storage device, comprising:
means to store data; and
a controller coupled to the means to store data, wherein the controller is configured to:
dynamically remap a range from a first portion of the means to store data to a second portion of the means to store data, wherein the second portion of the means to store data is a controller memory buffer (CMB);
maintain a module to hold lists of logical block address (LBA) to physical region page (PRP) relationships and LBA to the first portion relationships of data that has been pre-fetched;
receive a read command from a host device, wherein the read command has a logical block address (LBA);
forward the LBA to a LBA to dynamic random access memory (DRAM) (L2D) module; and
receive a physical region page (PRP) with the read command and send the PRP to the L2D module.
18 . The data storage device of claim 17 , wherein functionality of the module is by use of a content addressable memory (CAM) that is distinct from the means to store data.
19 . The data storage device of claim 17 , wherein the module is coupled to a CMB management module.
20 . The data storage device of claim 17 , wherein the L2D contains LBA to PRP information and LBA to DRAM address information.