Methods of testing repair circuits of memory devices
A method of testing a repair circuit of a memory device. The method may include storing first addresses in a first register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses, storing test addresses in a second register of the repair circuit, wherein the test addresses are provided from a test host, outputting hit signals by comparing bit values of the addresses stored in the first register with bit values of the addresses stored in the second register, outputting repair enable signals based on the hit signals, and determining a status of a path where the repair enable signals are generated based on logic levels of the repair enable signals.
1 . A method of testing a repair circuit of a memory device, the method comprising:
storing first addresses in a first register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and wherein the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses;
storing test addresses in a second register of the repair circuit, wherein the test addresses are provided from a test host;
outputting hit signals by comparing bit values of the first addresses stored in the first register with bit values of the test addresses stored in the second register;
outputting repair enable signals based on the hit signals; and
determining a status of a path where the repair enable signals are generated based on logic levels of the repair enable signals, wherein
the determining the status of the path where the repair enable signals are generated based on the logic levels of the repair enable signals comprises:
determining the status of the path as a fail when the first addresses match the test addresses and the repair enable signals have a first logic level; or
determining the status of the path as a fail when the first addresses do not match the test addresses and the repair enable signals have a second logic level that is different than the first logic level.
2 . The method of claim 1 , further comprising
providing the first addresses based on addresses provided from a test mode register set of the memory device.
3 . The method of claim 1 , wherein the storing of the test addresses in the second register of the repair circuit comprises sequentially providing, by the test host and as the test addresses, addresses of memory cell rows of each of memory banks included in a memory cell array.
4 . The method of claim 3 , wherein the outputting of the hit signals by comparing the bit values of the first addresses stored in the first register with the bit values of the test addresses stored in the second register comprises outputting the hit signals using XNOR logic circuits that each receive corresponding bit values of the addresses of the first and second registers.
5 . The method of claim 4 , wherein the determining the status of the path where the repair enable signals are generated based on the logic levels of the repair enable signals comprises:
determining the status of the path as a pass when the first addresses match the test addresses and the repair enable signals have the second logic level; or
determining the status of the path as a pass when the first addresses do not match the test addresses and the repair enable signals have the first logic level that is different than the second logic level.
6 . The method of claim 1 , wherein the storing of the test addresses in the second register of the repair circuit comprises providing, by the test host, addresses that are identical to the first addresses as the test addresses.
7 . The method of claim 6 , wherein the outputting of the hit signals by comparing the bit values of the addresses stored in the first register with the bit values of the addresses stored in the second register comprises outputting the hit signals using XNOR logic circuits that each receive corresponding bit values of the addresses of the first and second registers.
8 . The method of claim 7 , wherein the determining a status of the path where the repair enable signals are generated based on the logic levels of the repair enable signals comprises:
determining the status of the path as a pass when the repair enable signals have the second logic level; or
determining the status of the path as a fail when the repair enable signals have the first logic level.
9 . The method of claim 1 , further comprising monitoring logic levels of the repair enable signals in response to a delay strobe signal applied from the test host.
10 . The method of claim 9 , wherein the monitoring of the logic levels of the repair enable signals in response to the delay strobe signal applied from the test host comprises changing an application time of the delay strobe signal.
11 . A method of testing a repair circuit of a memory device, the method comprising:
presetting first addresses to a first register and a second register of the repair circuit, wherein the first register is configured to store faulty addresses during a normal operation of the memory device, and the repair circuit is configured to perform a repair operation to replace the faulty addresses with redundancy addresses;
providing test addresses to the second register, wherein the test addresses are provided from a test host and are addresses configured to cause repair enable signals output from the repair circuit to toggle;
outputting hit signals by comparing bit values of the first addresses stored in the first register with bit values of the test addresses stored in the second register;
outputting the repair enable signals based on the hit signals;
providing, by the test host, a hit signal pattern causing toggling of the repair enable signals to lines carrying the hit signals, and
determining a status of a path where the repair enable signals are generated based on the toggling of the repair enable signals.
12 . A memory device comprising:
a memory cell array including memory banks, wherein each of the memory banks includes a plurality of memory cells arranged at intersections of a plurality of rows and a plurality of columns, and redundancy memory cells for repairing faulty memory cells among the plurality of memory cells; and
for each of the memory banks, a repair circuit configured to include a plurality of unit circuits configured to generate repair enable signals that instruct a repair operation on the faulty memory cells,
wherein the unit circuits of the repair circuit comprise:
fail address memory including a first register and a second register, the first register configured to store first addresses and the second register configured to store test addresses, wherein the test addresses are provided from a test host;
a comparison circuit configured to output hit signals by comparing bit values of the first addresses stored in the first register with bit values of the test addresses stored the second register; and
a combinational logic circuit configured to output the repair enable signals based on the hit signals,
wherein a status of a path where the repair enable signals are generated is determined based on logic levels of the repair enable signals, and
wherein the determining the status of the path where the repair enable signals are generated based on the logic levels of the repair enable signals comprises:
determining the status of the path as a fail when the first addresses match the test addresses and the repair enable signals have a first logic level; or
determining the status of the path as a fail when the first addresses do not match the test addresses and the repair enable signals have a second logic level that is different than the first logic level.
13 . The memory device of claim 12 , wherein the repair circuit further comprises a counter circuit configured to output count addresses by sequentially incrementing addresses provided from a test mode register set of the memory device,
and respectively provides, as the first addresses, the count addresses output from the counter circuit to the plurality of unit circuits of the repair circuit.
14 . The memory device of claim 12 , wherein addresses of memory cell rows of each of the memory banks are sequentially provided to the test addresses.
15 . The memory device of claim 12 , wherein the test addresses are same as the first addresses.
16 . The memory device of claim 12 , wherein the test addresses are addresses configured to cause the repair enable signals to toggle.
17 . The memory device of claim 12 ,
wherein, for each of the memory banks, the repair circuit includes a first XOR logic circuit configured to receive the repair enable signal output from each of the plurality of unit circuits and output bank repair enable signals of the corresponding memory bank; and
a second XOR logic circuit configured to input the bank repair enable signals of each of the memory banks and output an all bank repair enable signal.
18 . The memory device of claim 17 ,
wherein the repair circuit further comprises a flip-flop (F/F) circuit configured to receive the bank repair enable signals,
wherein the F/F circuit is configured to output a delay output signal by latching the bank repair enable signals in response to a delay strobe signal applied from the test host, and
wherein the delay output signal is provided to the test host.