Method and apparatus for activating a remote device
View Patent ↗A system includes a first device to select and transmit a first code from a plurality of codes by a transmitter to a remote device controlling access. The remote device implements a switching device based on the received first code and generates a local sequence of data. The first device generates and transmits to the remote device a first sequence of signals based on the first code; the remote device processes the first sequence of signals and activates the mechanism based on the first sequence of signals and the local sequence of data. An n-state switching function with n=2{circumflex over ( )}k commutative involution is used in the switching device, the n-state commutative involution is not based on a XORing of 2 words of 2 bits with n and k being integers greater than 2. The first device may be a smartphone, a fob, an access card, or any other computing device.
1 . A computing device in communication with a receiving computing device, comprising:
a memory configured to store data including instructions;
a processor enabled to retrieve instructions from the memory and execute the instructions to perform the one or more steps of:
executing a computer operation selected from the group consisting of an encryption, a hashing, a sequence generation, wherein the computer operation includes an n-state commutative involution with n=2{circumflex over ( )}k that is a self-reversing 2 input operand n-state computer function for all n states and does not comply with all requirements of an addition over a finite field GF(n=2{circumflex over ( )}k) with n and k both being integers greater than 2;
creating a cryptographic message based on the computer operation; and
transmitting the cryptographic message on a physical transmission channel to the receiving computing device.
2 . The computing device of claim 1 , further comprising:
the memory configured to store a plurality of different sets of parameters, each set of parameters in the plurality of different sets of parameters determining the computer operation and each set of parameters corresponding to a unique code in a plurality of unique codes; and
the processor configured to activate a first set of parameters in the plurality of different sets of parameters and to perform the computer operation based on the first set of parameters and to transmit the cryptographic message and a first unique code corresponding to the first set of parameters to the receiving computing device.
3 . The computing device of claim 2 , further comprising:
the receiving computing device having a memory and a processor;
the processor of the receiving computing device configured to retrieve from the memory of the receiving computing device a first set of parameters based on the unique code received from the computing device and to generate data based on the first set of parameters; and
the processor of the receiving computing device configured to generate an opening instruction based on processing the cryptographic message received from the computing device and the data generated by the receiving computing device based on the received unique code.
4 . The computing device of claim 3 , wherein the opening instruction provides access to and/or activates at least one of the group consisting of a computer, a vehicle door controller, a garage door controller, an access controller, a server, an Automatic Teller Machine (ATM), a credit card server, a database, a database server, an order management server, a transaction server, and an Internet-of-Things (IoT) device controller.
5 . The computing device of claim 2 , wherein the processor of the receiving computing device is configured to disable the first set of parameters in the memory of the receiving computing device after the first set of parameters in the memory of the receiving computing device is activated.
6 . The computing device of claim 1 , wherein the computing device is selected from the group consisting of a computer, a mobile phone, a smart phone, a fob, an access card, a chipcard and a door opener.
7 . The computing device of claim 1 , further comprising instructions for the processor to modify the n-state commutative involution with a Finite Lab-Transform (FLT), the n-state commutative involution having at least a first input enabled to receive a first n-state operand and a second input enabled to receive a second n-state operand and an n-state output enabled to provide n-state output data, the FLT being characterized by the first input having an n-state reversible inverter not being identity to invert the first n-state operand and the second input having an n-state inverter identical to the n-state reversible inverter to invert the second n-state operand and the n-state output having a reversing n-state inverter to invert the n-state output data, the reversing n-state inverter in combination with the reversible n-state inverter establishing identity.
8 . The computing device of claim 1 , wherein the computer operation is an encryption in accordance with a modification of a specification of one of 1) an Advanced Encryption Standard (AES), 2) an Advanced Encryption Standard-Galois Counter Mode (AES-GCM) and 3) ChaCha20.
9 . The computing device of claim 1 , wherein the n-state commutative involution replaces a bitwise XOR of two words each being words of at least 8 bits.
10 . The computing device of claim 1 , wherein the n-state commutative involution is modified with an n-state Finite Lab-Transform (FLT), the n-state commutative involution having at least a first input enabled to receive a first n-state operand and a second input enabled to receive a second n-state operand and an n-state output enabled to provide n-state output data, the FLT being characterized by the first input having an n-state reversible inverter not being identity to invert the first n-state operand and the second input having an inverter identical to the n-state reversible inverter to invert the second n-state operand and the n-state output having a reversing n-state inverter to invert the n-state output data, the reversing n-state inverter in combination with the reversible n-state inverter establishing identity and wherein the n-state commutative involution that is modified with an n-state Finite Lab-Transform (FLT) combines a keystream with a plaintext of k bits.
11 . The computing device of claim 1 , wherein the computer operation is a hashing operation in accordance with a modification of a specification of one of 1) FIPS PUB 180-4, Secure Hash Standard (SHS), 2) FIPS PUB 202, SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions and 3) the MD5 Message-Digest Algorithm, Request for Comments: 7539; and the n-state commutative involution replaces a bitwise XOR of two words each being words of at least 8 bits.
12 . A cryptographic method, comprising:
executing by a processor of a computer operation selected from the group consisting of an encryption, a hashing, a sequence generation, wherein the computer operation includes an n-state commutative involution with n=2{circumflex over ( )}k that is a self-reversing 2 input operand n-state computer function for all n states and does not comply with all requirements of an addition over a finite field GF(n=2{circumflex over ( )}k) with n and k both being integers greater than 2;
creating by the processor of a cryptographic message based on the computer operation; and
transmitting the cryptographic message on a physical transmission channel to a receiving computing device.
13 . The method of claim 12 , further comprising:
storing by a memory of a plurality of different sets of parameters, each set of parameters in the plurality of different sets of parameters determining the computer operation and each set of parameters corresponding to a unique code in a plurality of unique codes; and
activating by the processor of a first set of parameters in the plurality of different sets of parameters and performing the computer operation based on the first set of parameters and transmitting the cryptographic message and a first unique code corresponding to the first set of parameters to the receiving computing device.
14 . The method of claim 13 , wherein the receiving computing device based on the cryptographic message, controls access to and/or activates at least one of the group consisting of a computer, a vehicle door controller, a garage door controller, an access controller, a server, an Automatic Teller Machine (ATM), a credit card server, a database, a database server, an order management server, a transaction server, and an Internet-of-Things (IoT) device controller.
15 . The method of claim 12 , further comprising instructions for the processor to modify the n-state commutative involution with a Finite Lab-Transform (FLT), the n-state commutative involution having at least a first input enabled to receive a first n-state operand and a second input enabled to receive a second n-state operand and an n-state output enabled to provide n-state output data, the FLT being characterized by the first input having an n-state reversible inverter not being identity to invert the first n-state operand and the second input having an n-state inverter being identical to the n-state reversible inverter to invert the second n-state operand and the n-state output having a reversing n-state inverter to invert the n-state output data, the reversing n-state inverter in combination with the reversible n-state inverter establishing identity.
16 . The method of claim 12 , wherein the computer operation is an encryption in accordance with a modification of a specification of at least one of: 1) an Advanced Encryption Standard (AES), 2) an Advanced Encryption Standard-Galois Counter Mode (AES-GCM) and 3) ChaCha20.
17 . The method of claim 12 , wherein the n-state commutative involution replaces in a standard computer implemented cryptographic operation a bitwise XOR of two words each being a word of at least k bits.
18 . The method of claim 12 , wherein the computer operation is modified with an n-state Finite Lab-Transform (FLT), the computer operation including the n-state commutative involution, and the n-state commutative involution having at least a first input enabled to receive a first n-state operand and a second input enabled to receive a second n-state operand and an n-state output enabled to provide n-state output data, the FLT being characterized by the first input having an n-state reversible inverter not being identity to invert the first n-state operand and the second input having an n-state inverter identical to the n-state reversible inverter to invert the second n-state operand and the n-state output having a reversing n-state inverter to invert the n-state output data, the reversing n-state inverter in combination with the reversible n-state inverter establishing identity and wherein the n-state commutative involution that is modified with an n-state Finite Lab-Transform (FLT) combines a keystream with a plaintext of k bits.
19 . The method of claim 12 , wherein the computer operation is a hashing operation in accordance with a modification of a specification of at least one: 1) FIPS PUB 180-4, Secure Hash Standard (SHS), FIPS PUB 202, 2) SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions and 3) the MD5 Message-Digest Algorithm, Request for Comments: 7539; and the n-state commutative involution replaces a bitwise XOR of two words each being a word of at least 8 bits.
20 . The method of claim 12 , wherein the n-state commutative involution is derived from a p-state commutative involution with p being an integer smaller than n.