IP Library › Granted Patent US 12,610,808
Granted Patent B2
US 12,610,808 · App. 17/545,996 · Granted Apr 21, 2026

Semiconductor structure including insulating vacancy for improving operation performance and method of fabricating the same

Inventors: Shang-Chun Chen (Hsinchu City, TW); Po-Chun Yeh (Taichung City, TW); Pei-Jer Tzeng (Hsinchu County, TW)
Assignee: Industrial Technology Research Institute
H01L23/5283H01L21/76816H01L21/7682H01L21/76831H01L23/5226H01L23/66H01L2223/6616H10D30/015H10D30/4755
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,610,808
App. No.
17/545,996
Granted
Apr 21, 2026
Kind
B2
Abstract

A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

Claims (29)

1 . A semiconductor structure, comprising:

a substrate, comprising a first surface, a second surface opposite to the first surface, an insulating vacancy extending from the first surface to the second surface, and a through hole passing through the substrate;

a conductive layer, filling in the through hole; and

a semiconductor device, disposed on the second surface and electrically connected to the conductive layer,

wherein the semiconductor device comprises a transistor having a gate, a channel layer and a source, the source is grounded through the conductive layer, and the insulating vacancy is located below the channel layer and the gate, the conductive layer in the through hole is not in contact with the channel layer of the transistor, and the insulating vacancy extends between the first and second surfaces of the substrate.

2 . The semiconductor structure according to claim 1 , wherein the source is in contact with a top surface of the conductive layer through a bottom surface of a contact plug, and an area of the top surface of the conductive layer is greater than or equal to an area of the bottom surface of the contact plug.

3 . The semiconductor structure according to claim 1 , wherein the source is electrically connected to the conductive layer through a contact plug, and a bottom surface of the contact plug is in contact with a top surface of the conductive layer.

4 . The semiconductor structure according to claim 1 , wherein the insulating vacancy extends from the first surface to the second surface to pass through the substrate.

5 . The semiconductor structure according to claim 4 , wherein a width of the through hole is less than or equal to a width of the insulating vacancy.

6 . The semiconductor structure according to claim 1 , wherein a width of the through hole is greater than a width of the insulating vacancy, and a depth of the insulating vacancy is less than a thickness of the substrate.

7 . The semiconductor structure according to claim 1 , further comprising:

a liner, wherein the liner is at least located between the substrate and the conductive layer.

8 . The semiconductor structure according to claim 1 , further comprising:

a support substrate, wherein the conductive layer is bonded to the support substrate.

9 . A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first surface and a second surface opposite to the first surface;

forming a semiconductor device on the second surface of the substrate, wherein the semiconductor device comprises a transistor having a gate, a channel layer and a source;

forming an insulating vacancy extending from the first surface to the second surface and a through hole passing through the substrate, wherein the insulating vacancy is located below the channel layer and the gate, a conductive layer in the through hole is not in contact with the channel layer of the transistor, and the insulating vacancy extends between the first and second surfaces of the substrate; and

forming the conductive layer in the through hole, wherein the source of the transistor is grounded through the conductive layer, and the semiconductor device is electrically connected to the conductive layer.

10 . The method of fabricating a semiconductor structure according to claim 9 , wherein the insulating vacancy and the through hole are formed after the semiconductor device is formed.

11 . The method of fabricating a semiconductor structure according to claim 10 , further comprising:

bonding the substrate on which the semiconductor device is formed to a carrier substrate, so that the semiconductor device is located between the substrate and the carrier substrate.

12 . The method of fabricating a semiconductor structure according to claim 9 , wherein the insulating vacancy and the through hole are formed in the substrate at the same time.

13 . The method of fabricating a semiconductor structure according to claim 9 , wherein a width of the through hole is less than or equal to a width of the insulating vacancy.

14 . The method of fabricating a semiconductor structure according to claim 9 , wherein a width of the through hole is greater than a width of the insulating vacancy, and a depth of the insulating vacancy is less than a thickness of the substrate.

15 . The method of fabricating a semiconductor structure according to claim 9 , further comprising:

forming a liner, wherein the liner is at least located between the substrate and the conductive layer.

16 . The method of fabricating a semiconductor structure according to claim 9 , further comprising:

providing a support substrate, and bonding the conductive layer to the support substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2021
From: CHEN, SHANG-CHUN; YEH, PO-CHUN; TZENG, PEI-JER
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Reel/Frame 058390/0728 →
Priority Claims (1)
TW 110141457 · Nov 8, 2021 · national
Continuity (1)
Related Publication 20230147806A1 · May 11, 2023
References Cited (35)
US 8026596B2 · Singhal et al. · 2011 [cited by applicant]
US 9318417B2 · Therrien et al. · 2016 [cited by applicant]
US 9536965B2 · Pei et al. · 2017 [cited by applicant]
US 10312358B2 · Ren et al. · 2019 [cited by applicant]
US 20050067716A1 · Mishra et al. · 2005 [cited by applicant]
US 20100295100A1 · Huang et al. · 2010 [cited by applicant]
US 20200395474A1 · Bothe et al. · 2020 [cited by applicant]
US 20220376085A1 · Bothe · 2022 [cited by examiner]
CN 103329256 · 2016 [cited by applicant]
CN 106169470 · 2016 [cited by applicant]
CN 111244050 · 2020 [cited by applicant]
CN 113555343 · 2021 [cited by applicant]
JP 2008117885 · 2008 [cited by applicant]
JP 2010067662 · 2010 [cited by applicant]
JP 2010080633 · 2010 [cited by applicant]
JP 2011192836 · 2011 [cited by applicant]
JP 2019537284 · 2019 [cited by applicant]
TW 560020 · 2003 [cited by applicant]
TW 200908273 · 2009 [cited by applicant]
TW 201118957 · 2011 [cited by applicant]
TW 201142999 · 2011 [cited by applicant]
TW I385788 · 2013 [cited by applicant]
TW 201438101 · 2014 [cited by applicant]
TW 201935695 · 2019 [cited by applicant]
TW 202137507 · 2021 [cited by applicant]
TW 202137514 · 2021 [cited by applicant]
TW 202320284 · 2023 [cited by applicant]
TW 202423216 · 2024 [cited by applicant]
“Office Action of Taiwan Counterpart Application”, issued on Oct. 19, 2022, p. 1-p. 5. [cited by applicant]
Abdalla Eblabla et al., “Membrane Supported GaN CPW Structures for High-frequency and High-power Applications,” 2019 IEEE Asia-Pacific Microwave Conference (APMC), Dec. 2019, pp. 1179-1181. [cited by applicant]
Ya-Hsi Hwang et al., “A Novel Approach to Improve Heat Dissipation of AlGaN/GaN High Electron Mobility Transistors with a Backside Cu via,” ECS Transactions, vol. 66, Apr. 2015, pp. 223-230. [cited by applicant]
Miao Yu et al., “Numerical Study on Microjet Cooling Structure for GaN HEMTs Integration on Silicon,” 2020 21st International Conference on Electronic Packaging Technology (ICEPT), Aug. 2020, pp. 1-6. [cited by applicant]
Kyu-Won Jang et al., “Thermal Analysis and Operational Characteristics of an AlGaN/GaN High Electron Mobility Transistor with Copper-Filled Structures: A Simulation Study,” Micromachines, Dec. 2019, pp. 1-13. [cited by applicant]
A. Bar-Cohen et al., “Embedded Cooling for Wide Bandgap Power Amplifiers: A Review,” Journal of Electronic Packaging, vol. 141, Dec. 2019, pp. 040803-1-040803-14. [cited by applicant]
Shawn S. H. Hsu et al., “GaN-on-silicon devices and technologies for RF and microwave applications,” 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Aug. 2016, pp. 1-3. [cited by applicant]