Reliability for DRAM device stack
An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.
1 . An integrated circuit stack, comprising:
an external command/address (CA) interface to receive commands and addresses from a device external to the integrated circuit stack;
a first memory device comprising at least a first memory array; and
a second memory device comprising at least a second memory, the second memory device electrically coupled to and stacked with the first memory device, wherein when the integrated circuit stack is in a first mode the first memory device and the second memory device to be addressable by a first chip identification value received via the external CA interface, and wherein when the integrated circuit stack is in a second mode, the first memory device is addressed by a second chip identification value and the second memory device is addressed by a third chip identification value that is not equal to the second chip identification value.
2 . The integrated circuit stack of claim 1 , wherein the first chip identification value is equal to the second chip identification value.
3 . The integrated circuit stack of claim 1 , wherein, the first memory integrated circuit is to store a plurality of check symbols.
4 . The integrated circuit stack of claim 1 , wherein, when the integrated circuit stack is in the first mode, the first chip identification value has a one bit less than the second chip identification value and a CA bit field used for the one bit carries a row address bit.
5 . The integrated circuit stack of claim 1 , wherein at least one of the first memory device and the second memory device are accessed via through-silicon vias communicating signals among devices of the integrated circuit stack.
6 . The integrated circuit stack of claim 5 , wherein first data signals communicated with the first memory device and second data signals communicated with the second memory device are communicated via different sets of through-silicon vias.
7 . The integrated circuit stack of claim 1 , wherein first data signals communicated with the first memory device and second data signals communicated with the second memory device are time-multiplexed on an external data (DQ) interface to communicate with the device external to the integrated circuit stack.
8 . The integrated circuit stack of claim 1 , wherein first data signals communicated with the first memory device and second data signals communicated with the second memory device are communicated on an external data (DQ) interface with the device external to the integrated circuit stack using different interface connections.
9 . An assembly, comprising:
an external command/address (CA) interface to receive commands and addresses from a device external to the assembly;
a first memory integrated circuit coupled to the external CA interface and comprising a first memory array; and
a second memory integrated circuit comprising a second memory array and being electrically coupled to and stacked with the first memory integrated circuit, the first memory integrated circuit configurable to, based on a first chip identification value associated with both the first memory integrated circuit and the second memory integrated circuit and received via the external CA interface, concurrently access both the first memory array of the first memory integrated circuit and the second memory array of the second memory integrated circuit.
10 . The assembly of claim 9 , where in the first chip identification value includes a bit that is used in determining a first plurality of cells to be accessed in the first memory array and a second plurality of cells to be accessed in the second memory array.
11 . The assembly of claim 9 , wherein, when the first memory integrated circuit is in a first mode, the first chip identification value concurrently accesses the first memory array and the second memory array.
12 . The assembly of claim 11 , wherein, when the first memory integrated circuit is in a second mode, the first memory integrated circuit is addressed by a second chip identification value and the second memory integrated circuit is addressed by a third chip identification value that is not equal to the second chip identification value.
13 . The assembly of claim 11 , further comprising:
a third memory integrated circuit comprising a third memory array and being electrically coupled to and stacked with the first memory integrated circuit and the second memory integrated circuit and the second memory integrated circuit and the third memory integrated circuit are accessed via through-silicon vias communicating signals among integrated circuits of the assembly.
14 . The assembly of claim 13 , wherein first data signals communicated with the second memory integrated circuit and second data signals communicated with the third memory integrated circuit are communicated among integrated circuits of the assembly using different sets of through-silicon vias.
15 . The assembly of claim 13 , wherein first data signals communicated with the second memory integrated circuit and second data signals communicated with the third memory integrated circuit are time-multiplexed on an external data (DQ) interface to communicate with the device external to the assembly.
16 . The assembly of claim 13 , wherein first data signals communicated with the second memory integrated circuit and second data signals communicated with the third memory integrated circuit are communicated on an external data (DQ) interface with the device external to the assembly using different interface connections.