IP Library › Granted Patent US 12,613,648
Granted Patent B2
US 12,613,648 · App. 18/599,209 · Granted Apr 28, 2026

Memory system for executing a target operation based on a program state of a super memory block and operating method thereof

Inventor: Young Soo Lim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F3/064G06F1/3296G06F3/0604G06F3/0673
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Quick Facts
Patent No.
US 12,613,648
App. No.
18/599,209
Granted
Apr 28, 2026
Kind
B2
Abstract

The embodiments of the present disclosure relate to a memory system and operating method thereof. According to embodiments of the present disclosure, the memory system may include i) a memory device including a plurality of memory blocks each including a plurality of pages, and ii) a memory controller configured to monitor a program operation on a first super memory block among a plurality of super memory blocks each including at least one of the plurality of memory blocks, and execute a target operation on the first super memory block based on the state of the first super memory block when it is determined that the program operation on the first super memory block has not been executed for a preset time period from a preset reference time point.

Claims (45)

1 . A memory system comprising:

a memory device including a plurality of memory blocks each including a plurality of pages; and

a memory controller configured to:

monitor a program operation on first memory blocks from among the plurality of memory blocks,

when it is determined that the program operation on the first memory blocks has not been executed for a preset time period, migrate valid data units stored in second memory blocks from among the plurality of memory blocks to the first memory blocks to fill at least one of the erased pages in the first memory blocks, and

count a number of erased pages for data to be written into, included in the first memory blocks,

wherein the memory controller is configured to migrate the valid data units in the second memory blocks to all the erased pages included in the first memory blocks when the number of the erased pages counted in the first memory blocks for the data to be written is less than a number of the valid data units stored in the second memory blocks,

wherein, after the number of erased pages is counted, the memory controller is configured to:

a) migrate the valid data units in the second memory blocks to a part of the first memory blocks when the number of erased pages counted in the first memory blocks available for the data to be written into is greater than or equal to a threshold number, and

b) migrate the valid data units in the second memory blocks to all of the erased pages included in the first memory blocks when the number of erased pages counted in the first memory blocks is less than the threshold number.

2 . The memory system of claim 1 , wherein the memory controller is configured to fill the valid data units into part of the erased pages in the first memory blocks.

3 . The memory system of claim 1 , wherein the memory controller is configured to fill the valid data units into all the erased pages in the first memory blocks.

4 . The memory system of claim 1 , wherein the memory controller is configured to determine whether to fill the valid data units into part of the erased pages in the first memory blocks or into all the erased pages in the first memory blocks based on i) the number of the erased pages in the first memory blocks or ii) whether the first memory blocks are memory blocks in which data is sequentially programmed.

5 . The memory system of claim 1 , wherein the memory controller is further configured to determine whether the program operation on the first memory blocks has not been executed for the time period from a time point at which the memory system enters an idle state or a low power mode.

6 . The memory system of claim 1 ,

wherein the memory controller is further configured to determine the preset size of the valid data units in proportion to a total size of the first memory blocks, and

wherein the total size of the first memory blocks is determined based on the number of the first memory blocks.

7 . The memory system of claim 6 , wherein the memory controller is configured to migrate the valid data units in the second memory blocks to the first memory blocks by reading the valid data units from the second memory blocks by an interleaved manner.

8 . The memory system of claim 7 , wherein the memory controller is configured to migrate the valid data units in the second memory blocks to the first memory blocks by programming the valid data units from a position next to a most recently programmed position in the first memory blocks.

9 . The memory system of claim 1 , wherein the memory controller is further configured to program, after the migrating the valid data units, data requested to be written from outside the memory system into an erased page included in the first memory blocks.

10 . A memory system comprising:

a memory device including a plurality of memory blocks each including a plurality of pages; and

a memory controller configured to:

monitor a program operation on first memory blocks from among the plurality of memory blocks,

when it is determined that the program operation on the first memory blocks has not been executed for a preset time period, migrate all valid data stored in the first memory blocks to second super memory blocks, and

count a number of erased pages for data to be written into, included in the first memory blocks,

wherein the memory controller is configured to migrate the valid data units in the second super memory blocks to all the erased pages included in the first memory blocks when the number of the erased pages counted in the first memory blocks for the data to be written is less than a number of the valid data units stored in the second super memory blocks,

wherein, after the number of erased pages is counted, the memory controller is configured to:

a) migrate the valid data units in the second memory blocks to a part of the first memory blocks when the number of erased pages counted in the first memory blocks available for the data to be written into is greater than or equal to a threshold number, and

b) migrate the valid data units in the second memory blocks to all of the erased pages included in the first memory blocks when the number of erased pages counted in the first memory blocks is less than the threshold number.

11 . An operating method of a memory system, the operating method comprising:

monitoring a program operation on first memory blocks from among a plurality of memory blocks each including a plurality of pages;

determining whether the program operation for the first memory blocks is executed for a preset time period;

when it is determined that the program operation on the first memory blocks has not been executed for a preset time period, migrating valid data units stored in second memory blocks from among the plurality of memory blocks to the first memory blocks to fill at least one of the erased pages in the first memory blocks, and

counting a number of erased pages for data to be written into, included in the first memory blocks,

wherein the migrating migrates the valid data units in the second memory blocks to all the erased pages included in the first memory blocks when the number of the erased pages counted in the first memory blocks for the data to be written is less than a number of the valid data units stored in the second memory blocks,

wherein, after the number of erased pages is counted, the migrating a) migrates the valid data units in the second memory blocks to a part of the first memory blocks when the number of erased pages counted in the first memory blocks available for the data to be written into is greater than or equal to a threshold number, and b) migrates the valid data units in the second memory blocks to all of the empty pages included in the first memory blocks when the number of erased pages counted in the first memory blocks is less than the threshold number.

12 . The operating method of claim 11 , wherein the migrating fills the valid data units into part of the erased pages in the first memory blocks.

13 . The operating method of claim 11 , wherein the migrating fills the valid data units into all the erased pages in the first memory blocks.

14 . The operating method of claim 11 , wherein the migrating determines whether to fill the valid data units into part of the erased pages in the first memory blocks or into all the erased pages in the first memory blocks based on i) the number of the erased pages in the first memory blocks or ii) whether the first memory blocks are memory blocks in which data is sequentially programmed.

15 . The operating method of claim 11 , wherein the determining determines whether the program operation on the first memory blocks has not been executed for the time period from time point at which the memory system enters an idle state or a low power mode.

16 . The operating method of claim 11 , further comprising determining the preset size of the valid data unit in proportion to a total size of the first memory blocks, and

wherein the total size of the first memory blocks is determined based on the number of first memory blocks.

17 . The operating method of claim 16 , wherein the migrating includes reading the valid data units from the second memory blocks by an interleaved manner.

18 . The operating method of claim 17 , wherein the migrating includes programming the valid data units from a position next to a most recently programmed position in the first memory blocks.

Priority Claims (1)
KR 10-2021-0183929 · Dec 21, 2021 · national
Continuity (2)
Continuation 17740437 · May 10, 2022
Related Publication 20240211153A1 · Jun 27, 2024
References Cited (12)
US 11586385B1 · Lercari · 2023 [cited by examiner]
US 20120023365A1 · Byom et al. · 2012 [cited by applicant]
US 20140013137A1 · Wilson et al. · 2014 [cited by applicant]
US 20180336127A1 · Hutchison · 2018 [cited by examiner]
US 20210109856A1 · Lee · 2021 [cited by examiner]
US 20210223976A1 · Zhu · 2021 [cited by examiner]
US 20220197790A1 · Palmer · 2022 [cited by examiner]
US 20220254434A1 · Yeung et al. · 2022 [cited by applicant]
US 20220269440A1 · Lin · 2022 [cited by applicant]
US 20230342293A1 · Du · 2023 [cited by examiner]
KR 102117919B1 · 2020 [cited by applicant]
KR 1020200113992A · 2020 [cited by applicant]