High speed RF switch method employing differential current cancellation
View Patent ↗A radio frequency (RF) switch employing differential signal cancellation is disclosed. The differential RF switch enables high isolation and extremely small size by employing cascode current steering within a differential switching amplifier. Unlike series RF switches, isolation with the differential RF switch is limited by device mismatch, not switch parasitic capacitance, enabling high frequency operation. Since the differential RF switch can be placed within the already present cascode devices, there is no additional insertion loss from the switch.
1 . A differential switching amplifier comprising:
positive and negative inverting input transistors adapted to receive corresponding positive and negative input voltages and to convert the corresponding positive and negative input voltages into respective negative and positive input currents;
positive and negative output terminals adapted to output corresponding positive and negative output currents;
a pair of always on cascode transistors, each of the pair of always on cascode transistors having a width of W/2, a first of the pair of always on cascode transistors adapted to couple half of the negative input current to the negative output terminal, a second of the pair of always on cascode transistors adapted to couple half of the positive input current to the positive output terminal;
a pair of enabled cascode transistors adapted to receive an enable gate signal (EN), each of the pair of enabled cascode transistors having a width of W/2, a first of the pair of enabled cascode transistors adapted to couple half of the negative input current to the negative output terminal when EN is high and to couple no current to the negative output terminal when EN is low, a second of the pair of enabled cascode transistors adapted to couple half of the positive input current to the positive output terminal when EN is high and to couple no current to the positive output terminal when EN is low;
a pair of bar enabled cascode transistors adapted to receive a bar enable gate signal (ENB), wherein ENB is a logical opposite of EN, each of the pair of bar enabled cascode transistors having a width of W/2, a first of the pair of bar enabled cascode transistors adapted to couple half of the negative input current to the positive output terminal when ENB is high and to couple no current to the positive output terminal when ENB is low, a second of the pair of bar enabled cascode transistors adapted to couple half of the positive input current to the negative output terminal when ENB is high and to couple no current to the negative output terminal when ENB is low; and
a pair of always off cascode transistors, each of the pair of always off cascode transistors having a width of W/2, a first of the pair of always off cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of always off cascode transistors coupled between the negative inverting input transistor and the positive output terminal.
2 . The differential switching amplifier of claim 1 , further comprising a current source device, the current source device coupled to corresponding sources of the positive and negative inverting input transistors, the current source device adapted to reject common mode signals.
3 . The differential switching amplifier of claim 2 , wherein the current source device is one of a transistor, an inductor, an LC tank circuit, or a resistor.
4 . The differential switching amplifier of claim 1 , further comprising a pair of calibrating cascode transistors, a first of the pair of calibrating cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of calibrating cascode transistors coupled between the negative inverting input transistor and the positive output terminal, the pair of calibrating cascode transistors adapted to cancel gain imbalance between the positive and negative output terminals.
5 . The differential switching amplifier of claim 1 , wherein the positive and negative input voltages correspond to a balanced input voltage.
6 . The differential switching amplifier of claim 1 , wherein the positive input voltage corresponds to an unbalanced input voltage and the negative input voltage corresponds to ground.
7 . An RF system comprising:
an antenna adapted to transmit and receive RF signals;
a baseband and processing element adapted to process baseband signals; and
receive and transmit differential switching amplifiers, the receive differential switching amplifier adapted to receive an RF signal from the antenna and to output an amplified/switched signal to the baseband and processing element, the transmit differential switching amplifier adapted to receive an RF signal from the baseband and processing element and to output an amplified/switched signal to the antenna, each of the receive and transmit differential switching amplifiers including:
positive and negative inverting input transistors adapted to receive corresponding positive and negative input voltages corresponding to an RF signal and to convert the corresponding positive and negative input voltages into respective negative and positive input currents;
positive and negative output terminals adapted to output corresponding positive and negative output currents;
a pair of always on cascode transistors, each of the pair of always on cascode transistors having a width of W/2, a first of the pair of always on cascode transistors adapted to couple half of the negative input current to the negative output terminal, a second of the pair of always on cascode transistors adapted to couple half of the positive input current to the positive output terminal;
a pair of enabled cascode transistors adapted to receive an enable gate signal (EN), each of the pair of enabled cascode transistors having a width of W/2, a first of the pair of enabled cascode transistors adapted to couple half of the negative input current to the negative output terminal when EN is high and to couple no current to the negative output terminal when EN is low, a second of the pair of enabled cascode transistors adapted to couple half of the positive input current to the positive output terminal when EN is high and to couple no current to the positive output terminal when EN is low; and
a pair of bar enabled cascode transistors adapted to receive a bar enable gate signal (ENB), wherein ENB is a logical opposite of EN, each of the pair of bar enabled cascode transistors having a width of W/2, a first of the pair of bar enabled cascode transistors adapted to couple half of the negative input current to the positive output terminal when ENB is high and to couple no current to the positive output terminal when ENB is low, a second of the pair of bar enabled cascode transistors adapted to couple half of the positive input current to the negative output terminal when ENB is high and to couple no current to the negative output terminal when ENB is low;
wherein each of the receive and transmit differential switching amplifiers further includes a pair of always off cascode transistors, each of the pair of always off cascode transistors having a width of W/2, a first of the pair of always off cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of always off cascode transistors coupled between the negative inverting input transistor and the positive output terminal.
8 . The RF system of claim 7 , wherein each of the receive and transmit differential switching amplifiers further includes a current source device, the current source device coupled to corresponding sources of the positive and negative inverting input transistors, the current source device adapted to reject common mode signals.
9 . The RF system of claim 8 , wherein the current source device is one of a transistor, an inductor, an LC tank circuit, or a resistor.
10 . The RF system of claim 7 , wherein each of the receive and transmit differential switching amplifiers further includes a pair of calibrating cascode transistors, a first of the pair of calibrating cascode transistors coupled between the positive inverting input transistor and the negative output terminal, a second of the pair of calibrating cascode transistors coupled between the negative inverting input transistor and the positive output terminal, the pair of calibrating cascode transistors adapted to cancel gain imbalance between the positive and negative output terminals.
11 . The RF system of claim 7 , wherein the positive and negative input voltages correspond to a balanced input RF signal.
12 . The RF system of claim 7 , wherein the positive input voltage corresponds to an unbalanced input RF signal and the negative input voltage corresponds to ground.
13 . The RF system of claim 7 , further comprising second receive and transmit differential switching amplifiers, the second receive differential switching amplifier adapted to receive the amplified/switched signal from the receive differential switching amplifier and to output a further amplified/switched signal to the baseband and processing element, the second transmit differential switching amplifier adapted to receive the amplified/switched signal from the transmit differential switching amplifier and to output a further amplified/switched signal to the antenna.
14 . The RF system of claim 13 , wherein each of the second receive and transmit differential switching amplifiers comprises:
second positive and negative inverting input transistors adapted to receive corresponding second positive and negative input voltages corresponding to the RF signal and to convert the corresponding second positive and negative input voltages into respective second negative and positive input currents;
second positive and negative output terminals adapted to output corresponding second positive and negative output currents;
a second pair of always on cascode transistors, each of the second pair of always on cascode transistors having a width of W/2, a first of the second pair of always on cascode transistors adapted to couple half of the second negative input current to the second negative output terminal, a second of the second pair of always on cascode transistors adapted to couple half of the second positive input current to the second positive output terminal;
a second pair of enabled cascode transistors adapted to receive a second enable gate signal (EN), each of the second pair of enabled cascode transistors having a width of W/2, a first of the second pair of enabled cascode transistors adapted to couple half of the second negative input current to the second negative output terminal when the second EN is high and to couple no current to the second negative output terminal when the second EN is low, a second of the second pair of enabled cascode transistors adapted to couple half of the second positive input current to the second positive output terminal when the second EN is high and to couple no current to the second positive output terminal when the second EN is low; and
a second pair of bar enabled cascode transistors adapted to receive a second bar enable gate signal (ENB), wherein the second ENB is a logical opposite of the second EN, each of the second pair of bar enabled cascode transistors having a width of W/2, a first of the second pair of bar enabled cascode transistors adapted to couple half of the second negative input current to the second positive output terminal when the second ENB is high and to couple no current to the second positive output terminal when the second ENB is low, a second of the second pair of bar enabled cascode transistors adapted to couple half of the second positive input current to the second negative output terminal when the second ENB is high and to couple no current to the second negative output terminal when the second ENB is low.