Driver circuit for controlling a semiconductor switch
In accordance with an embodiment, a method includes: operating a driver circuit in an idle mode in which portion of the driver circuit are deactivated, wherein the driver circuit is coupled to a first transistor and a second transistor coupled between a supply node and a first circuit node configured to be connected to a load, and operating the driver circuit in the idle mode comprises the driver circuit switching off the first transistor, switching on the second transistor; detecting a change in a voltage across the first transistor; and in response to the change in voltage being detected, activating the inactive portions of the driver circuit to switch on the first transistor and leave the idle mode.
1 . A circuit, comprising:
a first transistor coupled between a supply connection and a first circuit node configured to be connected to a load;
a second transistor coupled between the supply connection and the first circuit node;
a first circuit coupled to the first circuit node and configured to feed a current signal into the first circuit node or to discharge the current signal from the first circuit node;
a third transistor coupled between the supply connection and the first circuit node; and
a driver circuit coupled to the first transistor, the driver circuit configured to:
operate in an idle mode, in which portions of the driver circuit are inactive,
switch off the first transistor and switch on the second transistor while operating in the idle mode, and
detect a change in a voltage across the first transistor caused by the current signal in the idle mode,
activate the inactive portions of the driver circuit, switch on the first transistor, and leave the idle mode in response to the change in voltage being detected,
detect that a voltage across the first transistor reaches a second threshold value, and
turn on the third transistor in response to detecting that the voltage across the first transistor reaches the second threshold value.
2 . The circuit as claimed in claim 1 , wherein the first circuit comprises a controllable current source.
3 . The circuit as claimed in claim 1 , wherein the current signal comprises a current pulse with a defined amplitude.
4 . The circuit as claimed in claim 1 , wherein the first transistor is an n-channel field effect transistor and the second transistor is a p-channel field effect transistor.
5 . The circuit as claimed in claim 1 , further comprising:
a first comparator configured to detect that the voltage across the first transistor reaches a first threshold value, wherein the driver circuit is further configured to leave the idle mode in response to an output of the first comparator indicating that the voltage across the first transistor has reached the first threshold value.
6 . The circuit as claimed in claim 1 , further comprising:
a second comparator configured to detect that the voltage across the first transistor reaches the second threshold value, wherein a control electrode of the third transistor is coupled to an output of the second comparator.
7 . The circuit as claimed in claim 6 , wherein the third transistor is a p-channel field effect transistor.
8 . The circuit as claimed in claim 1 , further comprising a fourth transistor coupled between the supply connection and the first circuit node, wherein the driver circuit is configured to switch on the fourth transistor in response to the change in the voltage being detected.
9 . The circuit as claimed in claim 8 , wherein the fourth transistor comprises a control electrode coupled to a control electrode of the first transistor via a resistor.
10 . The circuit as claimed in claim 8 , wherein the first transistor and the fourth transistor are integrated in a same transistor cell array.
11 . The circuit as claimed in claim 1 , further comprising a fifth transistor coupled between the supply connection and a control electrode of the first transistor, wherein the driver circuit is designed to switch on the fifth transistor in response to the change in the voltage being detected.
12 . The circuit as claimed in claim 1 , wherein the first circuit is not part of the driver circuit.
13 . A method, comprising:
operating a driver circuit in an idle mode in which portions of the driver circuit are inactive, wherein the driver circuit is coupled to a first transistor and a second transistor coupled between a supply node and a first circuit node configured to be connected to a load, and operating the driver circuit in the idle mode comprises the driver circuit switching off the first transistor, switching on the second transistor;
generating a current signal;
feeding the current signal into the first circuit node or discharging the current signal from the first circuit node;
detecting a change in a voltage across the first transistor;
in response to the change in voltage being detected, activating inactive portions of the driver circuit to switch on the first transistor and leave the idle mode;
detecting that a voltage across the first transistor reaches a second threshold value; and
turning on a third transistor coupled between the supply node and the first circuit node in response to detecting that the voltage across the first transistor reaches the second threshold value.
14 . The method of claim 13 , further comprising:
detecting that a voltage across the first transistor reaches a first threshold value; and
leaving the idle mode in response to detecting that the voltage across the first transistor reaches the first threshold value.
15 . The method of claim 13 , further comprising:
turning on a fifth transistor coupled between the supply node and a control electrode of the first transistor in response to the change in voltage being detected.
16 . A circuit, comprising:
a gate driver circuit comprising:
a charge pump configured to be active during a normal operating mode and inactive during an idle mode,
a first output configured to activate a first transistor using an output of the charge pump during the normal operating mode, and deactivate the first transistor during the idle mode,
a second output configured to deactivate a second transistor during the normal operating mode and activate the second transistor during the idle mode,
a third output configured to activate and deactivate a third transistor,
a first comparator input port configured to be coupled to an output of a first comparator configured to compare a voltage across the first transistor to a first threshold,
a second comparator input port configured to be coupled to an output of a second comparator configured to compare a voltage across the first transistor to a second threshold, and
a logic circuit configured to:
transition the gate driver circuit from the idle mode to the normal operating mode in response to a signal at the first comparator input port indicating that the voltage across the first transistor has crossed the first threshold, and
activate the third transistor in response to a signal at the second comparator input port indicating that the voltage across the first transistor has crossed the second threshold.
17 . The circuit of claim 16 , further comprising:
the first transistor having a load path coupled between a power supply node and a first node configured to be coupled to a load, and a control input coupled to the first output;
the second transistor having a load path coupled between the power supply node and the first node, and a control node coupled to the second output; and
the first comparator having inputs coupled across the load path of the first transistor.
18 . The circuit of claim 17 , wherein:
the first transistor is an n-channel transistor; and
the second transistor is a p-channel transistor.
19 . The circuit of claim 17 , further comprising a controllable current source having an output coupled to the first node, wherein the controllable current source is configured to produce a current signal configured to cause the gate driver circuit to exit the idle mode by activating the first comparator.
20 . The circuit of claim 17 , further comprising the third transistor having a load path coupled between the power supply node and the first node, and a control node coupled to the third output.