Flexible self-aligned power via shape with gate cut first
A microelectronic device including a first nanosheet transistors adjacent to a second nanosheet transistor. The first nanosheet transistor includes a plurality of first nanosheets, and the second nanosheet transistor includes a plurality of second nanosheets. A source/drain located between the first nanosheet transistor and second nanosheet transistor. A first gate wraps around the plurality of first nanosheets. A second gate wraps around the plurality of second nanosheets. A first upper spacer located adjacent to the first gate, where the first upper spacer is in contact with at least three sides of the first gate. A second upper spacer located adjacent to the second gate, where the second upper spacer is in contact with at least three sides of the second gate. A backside interconnect connected to the source/drain, where the backside interconnect is in contact with the first upper spacer and the second upper spacer.
1 . A microelectronic device comprising:
a nanosheet transistor that includes a plurality of nanosheets;
a gate wrapped around the plurality of nanosheets;
an upper spacer located adjacent to the gate, wherein the upper spacer is in contact with at least three sides of the gate; and
a backside interconnect that is in contact with a first surface and a second surface of the upper spacer, wherein the first surface and the second surface are different surfaces.
2 . The microelectronic device of claim 1 , wherein the upper spacer includes a first section, a second section, and a third section, wherein the first section and the second section extend in a direction parallel to a gate direction.
3 . The microelectronic device of claim 2 , wherein the third section of the upper spacer extends perpendicular to the gate direction.
4 . The microelectronic device of claim 3 , further comprising:
a shallow trench isolation layer located beneath the gate; and
a gate cap located above the gate.
5 . The microelectronic device of claim 4 , wherein the third section of the upper spacer extends from the shallow trench isolation layer to the gate cap, wherein the third section of the upper spacer is in contact with the shallow trench isolation layer, the gate, and the gate cap.
6 . A microelectronic device comprising:
a first nanosheet transistors adjacent to a second nanosheet transistor, wherein the first nanosheet transistor includes a plurality of first nanosheets, wherein the second nanosheet transistor includes a plurality of second nanosheets;
a source/drain located between the first nanosheet transistor and second nanosheet transistor;
a first gate wraps around the plurality of first nanosheets;
a second gate wraps around the plurality of second nanosheets;
a first upper spacer located adjacent to the first gate, wherein the first upper spacer is in contact with at least three sides of the first gate;
a second upper spacer located adjacent to the second gate, wherein the second upper spacer is in contact with at least three sides of the second gate;
a backside interconnect connected to the source/drain, wherein the backside interconnect is in contact with the first upper spacer and the second upper spacer, wherein the backside interconnect is in contact with a first surface and a second surface of the first upper spacer, wherein the first surface and the second surface are different surfaces, wherein the backside interconnect is in contact with a third surface and a fourth surface of the second upper spacer, wherein the third surface and the fourth surface are different surfaces.
7 . The microelectronic device of claim 6 , wherein the first upper spacer includes a first section, a second section, and a third section, wherein the second upper spacer includes a fourth section, a fifth section, and a sixth section, wherein the first section, the second section, the fourth section, and the fifth section extend parallel to a gate direction.
8 . The microelectronic device of claim 7 , wherein the third section and the sixth section extends perpendicular to the gate direction.
9 . The microelectronic device of claim 8 , further comprising:
a shallow trench isolation layer located beneath the first gate and beneath the second gate; and
a gate cap located above the first gate and the second gate.
10 . The microelectronic device of claim 9 , wherein the third section of the first upper space and the sixth section of the second upper spacer extends from the shallow trench isolation layer to the gate cap, wherein the third section of the first upper spacer is in contact with the shallow trench isolation layer, the first gate, and the gate cap, and wherein the sixth section of the second upper spacer is in contact with the shallow trench isolation layer, the second gate, and the gate cap.
11 . The microelectronic device of claim 10 , wherein the backside interconnect includes a protrusion section and a horizontal section.
12 . The microelectronic device of claim 11 , wherein the protrusion section extends in parallel to the gate direction and the horizontal section extends perpendicular to the gate direction.
13 . The microelectronic device of claim 12 , wherein the protrusion section is in contact with the second section of the first upper spacer and the protrusion section is in contact with the fourth section of the second upper spacer.
14 . The microelectronic device of claim 13 , wherein the horizontal section is in contact with the third section of the first upper spacer and the horizontal section is in contact with the sixth section of the second upper spacer.
15 . The microelectronic device of claim 12 , wherein the horizontal section and the protrusion section extend to a backside of the first and second nanosheet transistors.
16 . The microelectronic device of claim 15 , wherein the horizontal section has a first width as it extends towards the backside of the first and second nanosheet transistor, wherein the first width is measure in parallel with the gate direction.
17 . The microelectronic device of claim 16 , wherein the protrusion section has a second width as it extends towards the backside of the first and second nanosheet transistor, wherein the second width is measured in parallel with the gate direction.
18 . The microelectronic device of claim 17 , wherein the second width is larger than the first width.