Three-dimensional fan-out integrated package structure, packaging method thereof, and wireless headset
A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 μm/1.5 μm. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.
1 . A method for preparing a three-dimensional fan-out integrated packaging structure, comprising following operation steps:
providing a support substrate, and forming a separation layer on the support substrate;
forming a second rewiring layer on the separation layer, wherein the second rewiring layer comprises a second dielectric layer and a second metal wire layer disposed in the second dielectric layer,
forming a plurality of metal connection pillars on the second rewiring layer and at sides of a first semiconductor chip and second semiconductor chip stacked together, and electrically connected to the second rewiring layer;
wherein the second semiconductor chip has a first surface and a second surface, and the second surface of the second semiconductor chip is bonded to the second rewiring layer,
wherein the first semiconductor chip has a first surface and a second surface, wherein the second surface of the first semiconductor chip is stacked on the first surface of the second semiconductor chip with a metal conductive layer in between; and wherein the first semiconductor chip is electrically connected to the second semiconductor chip through the metal conductive layer;
forming a first filler layer in a gap in the metal conductive layer of the stack of the first semiconductor chip and the second semiconductor chip;
forming a first encapsulating layer on the second rewiring layer, wherein the first encapsulating layer encapsulates the plurality of metal connection pillars, the first semiconductor chip, and the second semiconductor chip;
forming a first rewiring layer on the first encapsulating layer, wherein the first rewiring layer comprises a first dielectric layer and a first metal wire layer disposed in the first dielectric layer, and electrically connecting the first metal wire layer to the second semiconductor chip and the plurality of metal connection pillars;
wherein the second rewiring layer is configured to be on the first surface of the second semiconductor chip, wherein the second rewiring layer and the first rewiring layer are parallel and located on opposite sides of the stacked first semiconductor chip and second semiconductor chip;
forming metal bumps on a surface of the first rewiring layer away from the stacked first semiconductor chip and second semiconductor chip, and electrically connecting the metal bumps to the first metal wire layer,
providing a carrier, and flipping the three-dimensional fan-out integrated packaging structure upside down on the carrier,
peeling off the support substrate at the separation layer, to expose a surface of the second rewiring layer away from the stacked first semiconductor chip and second semiconductor chip;
providing a plurality of functional chips on said exposed surface of the second rewiring layer, and electrically connecting the plurality of functional chips to the second metal wire layer,
forming a second filler layer in a gap between the plurality of functional chips and the second rewiring layer,
forming a second encapsulating layer on the surface of the second rewiring layer away from the stacked first semiconductor chip and second semiconductor chip, wherein the second encapsulating layer encapsulates the plurality of functional chips; and
removing the carrier.
2 . The method according to claim 1 , wherein the support substrate is selected from a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; the carrier is selected from a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate; wherein the separation layer is selected from a tape layer or polymer layer, and wherein the separation layer is applied to a surface of the support substrate by a spin coating process, and then the separation layer is cured into a solid film using a laser curing, UV curing, or thermal curing process.
3 . The method according to claim 1 , wherein the forming of the first rewiring layer and the second rewiring layer comprises:
forming a first dielectric layer and a second dielectric layer using a chemical vapor deposition process or a physical vapor deposition process, etching the first deposited dielectric layer to form a pattemed first dielectric layer, and etching the second deposited dielectric layer to form a patterned second dielectric layer; and
forming a first metal layer on a top surface of the first dielectric layer and a second metal layer on a top surface of the second dielectric layer using a chemical vapor deposition process, a physical vapor deposition process, an evaporation plating process, a sputtering process, an electroplating process or a chemical plating process, etching the first metal layer to form the first metal wire layer, etching the second metal layer to form the second metal wire layer, and electrically connecting the first metal wire layer to the second metal wire layer through the plurality of metal connection pillars.