Semiconductor package including a semiconductor chip on a redistribution substrate and conductive structure spaced apart from the semiconductor chip
A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.
1 . A semiconductor package comprising:
a first redistribution substrate;
a semiconductor chip on a top surface of the first redistribution substrate;
a conductive structure on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip;
a molding layer on the first redistribution substrate and on a side surface of the semiconductor chip and a side surface of the conductive structure; and
a second redistribution substrate on the molding layer and the conductive structure,
wherein the conductive structure comprises:
a first conductive structure on the first redistribution substrate; and
a second conductive structure on a top surface of the first conductive structure and including nickel,
wherein the second redistribution substrate comprises an insulating layer, and
wherein the insulating layer directly contacts at least a portion of a top surface of the second conductive structure and at least a portion of a top surface of the molding layer.
2 . The semiconductor package of claim 1 , wherein the top surface of the molding layer is coplanar with the top surface of the second conductive structure.
3 . The semiconductor package of claim 1 , wherein the second conductive structure directly contacts the first conductive structure, and
wherein the second conductive structure is on the top surface of the first conductive structure.
4 . The semiconductor package of claim 1 , wherein the first conductive structure overlaps the second conductive structure when viewed in a plan view.
5 . The semiconductor package of claim 1 , wherein the first conductive structure has a first height and the second conductive structure has a second height that is less than the first height.
6 . The semiconductor package of claim 5 , wherein the second height is in a range from 10 μm to 30 μm.
7 . The semiconductor package of claim 1 , wherein a width of the first conductive structure is substantially equal to a width of the second conductive structure.
8 . The semiconductor package of claim 1 , further comprising:
a seed pattern between the first conductive structure and the first redistribution substrate.
9 . The semiconductor package of claim 8 , wherein a width of the seed pattern is substantially equal to a width of the first conductive structure.
10 . The semiconductor package of claim 1 , further comprising:
bumps between the first redistribution substrate and the semiconductor chip,
wherein the first redistribution substrate is electrically connected to the semiconductor chip through the bumps.
11 . The semiconductor package of claim 1 , wherein the top surface of the first conductive structure has a shape which is convex or concave with respect to the top surface of the first redistribution substrate.
12 . A semiconductor package comprising:
a first redistribution substrate;
a semiconductor chip on a top surface of the first redistribution substrate;
a conductive structure on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip;
a molding layer on the first redistribution substrate and on a side surface of the semiconductor chip and a side surface of the conductive structure; and
a second redistribution substrate on the molding layer and the conductive structure and connected to the conductive structure,
wherein the conductive structure comprises:
a first conductive structure connected to the first redistribution substrate; and
a second conductive structure on the first conductive structure,
wherein the second conductive structure includes nickel,
wherein a top surface of the second conductive structure is coplanar with a top surface of the molding layer,
wherein the second redistribution substrate comprises an insulating layer, and
wherein the insulating layer directly contacts at least a portion of the top surface of the second conductive structure and at least a portion of the top surface of the molding layer.
13 . The semiconductor package of claim 12 , wherein the first conductive structure has a first height and the second conductive structure has a second height that is less than the first height, and
wherein the second height is in a range from 10 μm to 30 μm.
14 . The semiconductor package of claim 12 , further comprising:
a bonding pad between the first redistribution substrate and the conductive structure,
wherein the bonding pad comprises gold (Au).
15 . The semiconductor package of claim 12 , wherein the second conductive structure directly contacts the first conductive structure, and
wherein the second conductive structure is on a top surface of the first conductive structure.
16 . The semiconductor package of claim 12 , further comprising:
an upper semiconductor chip on a top surface of the second redistribution substrate.
17 . A semiconductor package comprising:
a first redistribution substrate comprising a first insulating layer and a first redistribution pattern;
a solder ball on a bottom surface of the first redistribution substrate;
a semiconductor chip on a top surface of the first redistribution substrate;
a conductive structure on the first redistribution substrate and laterally spaced apart from the semiconductor chip;
a seed pattern disposed between the first redistribution substrate and the conductive structure;
a molding layer on the first redistribution substrate and on the semiconductor chip, the molding layer on a side surface of the conductive structure and exposing a top surface of the conductive structure; and
a second redistribution substrate on the molding layer and connected to the conductive structure,
wherein the second redistribution substrate comprises a second insulating layer and a second redistribution pattern,
wherein the conductive structure comprises:
a first conductive structure on the top surface of the first redistribution substrate; and
a second conductive structure on a top surface of the first conductive structure,
wherein the second insulating layer comprises a photosensitive polymer,
wherein the second conductive structure comprises nickel (Ni), and
wherein the second insulating layer directly contacts at least a portion of a top surface of the second conductive structure and at least a portion of a top surface of the molding layer.
18 . The semiconductor package of claim 17 , further comprising:
a bonding pad disposed between the first redistribution pattern and the first conductive structure,
wherein the bonding pad comprises gold (Au).
19 . The semiconductor package of claim 17 , wherein a width of the first conductive structure is substantially equal to a width of the second conductive structure, and
wherein a height of the first conductive structure is greater than a height of the second conductive structure.