IP Library › Granted Patent US 12,620,950
Granted Patent B2
US 12,620,950 · App. 18/307,089 · Granted May 5, 2026

Power amplifier circuit

Inventors: Shohei Imai (Kyoto, JP); Satoshi Tanaka (Kyoto, JP)
Assignee: Murata Manufacturing Co., Ltd.
H03F3/245H03F1/56H03F2200/09
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Quick Facts
Patent No.
US 12,620,950
App. No.
18/307,089
Granted
May 5, 2026
Kind
B2
Abstract

A power amplifier circuit includes: a power splitter; a first amplifier; a second amplifier; a first balun that splits a first amplified signal into a third amplified signal and a fourth amplified signal having a different phase from the third amplified signal; a third amplifier and a fourth amplifier that respectively amplify the third amplified signal and the fourth amplified signal; a second balun that splits a second amplified signal into a fifth amplified signal and a sixth amplified signal having a different phase from the fifth amplified signal; a fifth amplifier that amplifies the fifth amplified signal if a power level of the fifth amplified signal is equal to or higher than a predetermined power level; and a sixth amplifier that amplifies the sixth amplified signal if a power level of the sixth amplified signal is equal to or higher than a predetermined power level.

Claims (34)

1 . A power amplifier circuit comprising:

a power splitter configured to split an input signal into a first signal and a second signal having a different phase from the first signal;

a first amplifier configured to amplify the first signal and to output a first amplified signal;

a second amplifier configured to amplify the second signal and to output a second amplified signal;

a first balun configured to split the first amplified signal into a third amplified signal and a fourth amplified signal having a different phase from the third amplified signal;

a third amplifier configured to amplify the third amplified signal;

a fourth amplifier configured to amplify the fourth amplified signal;

a second balun configured to split the second amplified signal into a fifth amplified signal and a sixth amplified signal having a different phase from the fifth amplified signal;

a fifth amplifier configured to amplify the fifth amplified signal when a power level of the fifth amplified signal is equal to or greater than a first predetermined power level; and

a sixth amplifier configured to amplify the sixth amplified signal when a power level of the sixth amplified signal is equal to or greater than a second predetermined power level.

2 . The power amplifier circuit according to claim 1 ,

wherein the power amplifier circuit is on a single semiconductor substrate, and

wherein the first balun or the second balun comprises a terminal configured to externally connect the semiconductor substrate.

3 . The power amplifier circuit according to claim 1 ,

wherein the power splitter does not comprise a terminal grounded through a resistor.

4 . The power amplifier circuit according to claim 1 ,

wherein the power splitter comprises a terminal grounded through a resistor.

5 . The power amplifier circuit according to claim 4 , wherein the power splitter comprises:

a first inductor having a first end to which the input signal is supplied and a second end that supplies the first signal;

a second inductor electromagnetically coupled to the first inductor and having a first end that is the terminal, and a second end that supplies the second signal;

a first capacitor having a first end connected to the first end of the first inductor, and a second end connected to the first end of the second inductor; and

a second capacitor having a first end connected to the second end of the first inductor, and a second end connected to the second end of the second inductor.

6 . The power amplifier circuit according to claim 1 ,

wherein the first balun is on a semiconductor substrate and comprises a third capacitor, and

wherein the first balun is connected to an output terminal of the first amplifier and comprises a terminal configured to externally connect the semiconductor substrate through the third capacitor.

7 . The power amplifier circuit according to claim 1 ,

wherein the second balun is on a semiconductor substrate and comprises a fourth capacitor, and

wherein the second balun is connected to an output terminal of the second amplifier and comprises a terminal configured to externally connect the semiconductor substrate through the fourth capacitor.

8 . The power amplifier circuit according to claim 1 , further comprising:

a power combiner configured to combine amplified signals respectively output from the third amplifier, the fourth amplifier, the fifth amplifier, and the sixth amplifier,

wherein a first part of the power combiner comprises a semiconductor substrate, and second part of the power combiner comprises a module substrate.

9 . The power amplifier circuit according to claim 8 ,

wherein a part of the power combiner comprises a lumped constant circuit element, and

wherein at least a part of the lumped constant circuit element is a surface mount device mounted on the module substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2024
From: IMAI, SHOHEI; TANAKA, SATOSHI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 066109/0769 →
Priority Claims (1)
JP 2020-179858 · Oct 27, 2020 · national
Continuity (2)
Continuation PCTJP2021039036 · Oct 22, 2021
Related Publication 20230261622A1 · Aug 17, 2023
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