IP Library › Granted Patent US 12,620,984
Granted Patent B2
US 12,620,984 · App. 18/423,567 · Granted May 5, 2026

Semiconductor device

Inventor: Yuki Kumazawa (Matsumoto-city, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H03K17/0828H03K17/14H03K2017/0806H03K2217/0027
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Quick Facts
Patent No.
US 12,620,984
App. No.
18/423,567
Granted
May 5, 2026
Kind
B2
Abstract

A semiconductor device includes a switching element performing a switching base on an input signal to operate a load, a detection circuit outputting a release signal upon detecting a predetermined state of the switching element, and a driving current control circuit including a latch circuit that latches a detection result obtained from a magnitude of a current flowing through the switching element and to be reset upon receiving the release signal from the detection circuit. The control circuit outputs, based on an output of the latch circuit a first driving current or a second driving current larger than the first driving current. The driving current is used for charging a gate capacitance of the switching element in an operation state of the semiconductor device. The control circuit sets the driving current to the first driving current upon the latch circuit being reset by the release signal.

Claims (44)

1 . A semiconductor device, comprising:

a switching element configured to perform a switching on a basis of an input signal to operate a load;

a detection circuit configured to output a release signal upon detecting a predetermined state of the switching element; and

a driving current control circuit including a latch circuit configured to latch a data signal that depends on a magnitude of a current flowing through the switching element and to output a latched data signal in accordance with the input signal,

wherein the driving current control circuit is configured to output, on a basis of an output of the latch circuit, a driving current for charging a gate capacitance of the switching element in an operation state of the semiconductor device,

wherein the latch circuit is configured to receive the release signal from the detection circuit and to reset the output thereof upon receiving the release signal from the detection circuit, and

wherein the driving current control circuit sets the driving current such that:

(i) upon detecting that a current flowing through the switching element is less than a switching current value, the driving current control circuit sets the driving current to a first driving current;

(ii) upon detecting that the current flowing through the switching element is greater than the switching current value, the driving current control circuit sets the driving current to a second driving current that is larger than the first driving current; and

(iii) upon the latch circuit receiving the release signal, the driving current control circuit sets the driving current to the first driving current.

2 . The semiconductor device according to claim 1 , wherein:

the predetermined state is at least one of an overcurrent state of the switching element in which an overcurrent flows through the switching element, an overheat state of the switching element in which the switching element is overheated, or a device power source voltage drop state in which a power voltage of the semiconductor device is lower than a predetermined level; and

the detection circuit, upon detecting the predetermined state, outputs the release signal to the latch circuit, the release signal being also output to an outside of the semiconductor device to inform the predetermined state being detected, and being used to stop driving of the switching element.

3 . The semiconductor device according to claim 1 , wherein:

the predetermined state is an overcurrent state of the switching element in which an overcurrent flows through the switching element; and

the detection circuit, upon detecting the overcurrent state, outputs the release signal to the latch circuit, the release signal being also used to stop driving of the switching element.

4 . The semiconductor device according to claim 1 , wherein:

the predetermined state is an overcurrent state of the switching element in which a current flowing through the switching element is equal to or greater than a predetermined current; and

the detection circuit, upon detecting the overcurrent state, outputs the release signal to the latch circuit.

5 . The semiconductor device according to claim 1 , wherein:

the predetermined state is a state in which the current flowing through the switching element is equal to or greater than a predetermined current and in which a driving voltage input to the switching element is equal to or greater than a predetermined voltage; and

the detection circuit, upon detecting the predetermined state, outputs the release signal to the latch circuit.

6 . The semiconductor device according to claim 1 , wherein the driving current control circuit further includes

a switching current detection circuit configured to detect whether or not the current flowing through the switching element is greater than the switching current value, and output a first switching signal in response to detecting that the current is less than the switching current value and a second switching signal in response to detecting that the current is greater than the switching current value, the latch circuit latching the detection result obtained from the first or second switching signal;

a selection circuit configured to output, on a basis of the output from the latch circuit, a selection signal for setting the driving current to either the first driving current or the second driving current; and

a driving current output circuit configured to output the first driving current or the second driving current on a basis of the selection signal.

7 . The semiconductor device according to claim 6 , wherein:

the latch circuit, on a basis of the input signal, latches the detection result obtained from the first or second switching signal to output the detection result as the output of the latch circuit, or outputs a latch release output signal as the output of the latch circuit upon receiving the release signal,

the selection circuit outputs a first selection signal upon receiving the output of the latch circuit obtained from the first switching signal or upon receiving the latch release output signal, and outputs a second selecting signal upon receiving the output of the latch circuit obtained from the second switching signal, and

to charge the gate capacitance of the switching element, the driving current output circuit outputs the first driving current upon receiving the first selection signal or the latch release output signal and outputs the second driving current upon receiving the second selection signal.

8 . The semiconductor device according to claim 6 , wherein

the switching element is included in one of upper arm and lower arm, and

a boundary value between a first current region, when the first current region includes a maximum value of a voltage change rate of a switching element of the other one of the upper arm and lower arm when a diode of the other arm performs a recovery operation when the switching element of the one arm is turned on, of the current flowing through the switching element of the one arm and a second current region, when the second current region does not include the maximum value, and of the current flowing through the switching element of the one arm is set as the switching current value.

9 . A semiconductor device, comprising:

a switching element configured to perform a switching on a basis of an input signal to operate a load;

a state detection circuit configured to output a release signal upon detecting a predetermined state of the switching element; and

a driving current control circuit including

a switching current detection circuit configured to detect whether or not a current flowing through the switching element is greater than a switching current value, and

a latch circuit configured to latch a data signal that depends on a magnitude of the current flowing through the switching element and to output a latched data signal in accordance with the input signal, wherein the driving current control circuit is configured to output, on a basis of an output of the latch circuit, a driving current for charging a gate capacitance of the switching element in an operation state of the semiconductor device,

wherein the latch circuit is configured to receive the release signal from the state detection circuit and to reset the output thereof upon receiving the release signal from the state detection circuit, and

wherein the driving current control circuit sets the driving current such that:

(i) upon the switching current detection circuit detecting that the current flowing through the switching element is less than a switching current value, the driving current control circuit sets the driving current to a first driving current;

(ii) upon the switching current detection circuit detecting that the current flowing through the switching element is greater than the switching current value, the driving current control circuit sets the driving current to a second driving current that is larger than the first driving current; and

(iii) upon the latch circuit receiving the release signal output from the state detection circuit, the driving current control circuit sets the driving current to the first driving current.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2024
From: KUMAZAWA, YUKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 066258/0415 →
Priority Claims (1)
JP 2023-042470 · Mar 17, 2023 · national
Continuity (1)
Related Publication 20240313763A1 · Sep 19, 2024
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