HD3 cancellation technique in RF DACs and digital transmitters
A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.
1 . An apparatus, comprising:
a first circuit configured to generate multiphase pulses; and
a second circuit configured to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses,
wherein:
the multiphase pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle,
wherein the first circuit is configured to generate the multiphase pulses having the duty cycle such that a first null appears at a third harmonic frequency of the pulse, and
wherein the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55%.
2 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with the duty cycle within 30-35% such that the first null appears at the third harmonic frequency of the pulse to enable rejection of a third harmonic distortion (HD3).
3 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with the duty cycle within 45-55%.
4 . The apparatus of claim 3 , wherein the second circuit comprises a digital four-phase in-phase (I) and quadrature (Q) mixer and is configured to use the set of four-phase LO pulses.
5 . The apparatus of claim 1 , wherein the second circuit is further configured to mix the set of I-data and Q-data with the multiphase pulses to generate an output radio frequency (RF) signal.
6 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with a phase difference of 90 degrees.
7 . The apparatus of claim 6 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.
8 . An integrated circuit, comprising:
a first circuit configured to generate a set of multiphase pulses with duty cycles; and
a second circuit configured to receive the set of multiphase pulses and reject a third harmonic distortion (HD3) of the set of multiphase pulses, wherein
the multiphase pulses comprise multiple in-phase (I) pulses and multiple quadrature (Q) pulses each comprising a pulse having a duty cycle, and
the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55% to reject the HD3.
9 . The integrated circuit of claim 8 , wherein:
the set of multiphase pulses include a set of four-phase LO pulses, and wherein
the second circuit comprises a mixer circuit configured to use the set of four-phase LO pulses to reject the HD3 and a third counter intermodulation (CIM3) of the set of multiphase pulses.
10 . The integrated circuit of claim 8 , wherein the set of multiphase pulses comprise a set of four-phase LO pulses with a phase difference of 90 degrees.
11 . The integrated circuit of claim 10 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.
12 . A communication device, comprising:
a first circuit configured to generate a set of four-phase LO pulses; and
a second circuit configured to mix in-phase (I) data and quadrature (Q) data with the set of four-phase LO pulses,
wherein the first circuit is further configured to generate the set of four-phase LO pulses with duty cycles such that a first null of a frequency spectrum of a pulse of the set of four-phase LO pulses occurs at a third harmonic frequency,
the four-phase LO pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle, and
the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the four-phase LO pulses to be within 30-35% or within 45-55%.
13 . The communication device of claim 12 , wherein the second circuit comprises a digital four-phase in-phase (I) and quadrature (Q) mixer circuit and is configured to use the set of four-phase LO pulses to improve a third harmonic distortion (HD3) and a third counter intermodulation (CIM3) of the pulse of the set of four-phase LO pulses.
14 . The communication device of claim 13 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.