Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.
1 . A semiconductor package, comprising:
a package substrate;
a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip comprising a free end portion;
conductive wires respectively electrically connecting chip pads of the first semiconductor chips to substrate pads of the package substrate; and
a plurality of first support structures, each having a first end attached to the upper surface of the package substrate and an opposite second end with an end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate.
2 . The semiconductor package of claim 1 , wherein at least one of the chip pads of the uppermost semiconductor chip is on an upper surface of the free end portion, and
wherein the second ends of the first support structures supports are attached to a lower surface of the free end portion.
3 . The semiconductor package of claim 1 , wherein each of the first support structures comprises:
a wire bonding portion on the package substrate; and
a dummy wire having a first end joined to the wire bonding portion and an opposite second end contacting a lower surface of the free end portion.
4 . The semiconductor package of claim 1 , further comprising:
at least one second semiconductor chip on the uppermost semiconductor chip of the plurality of first semiconductor chips, the at least one second semiconductor chip comprising a free end portion; and
a plurality of second support structures, each having a first end attached to an upper surface of one of the plurality of first semiconductor chips and an opposite second end attached to the free end portion of the at least one second semiconductor chip.
5 . The semiconductor package of claim 1 , further comprising:
a plurality of second semiconductor chips stacked on the first semiconductor chips in a stair-step configuration opposite to the stair-step configuration of the first semiconductor chips, the plurality of second semiconductor chips having an uppermost semiconductor chip at a second height from an upper surface one of the first semiconductor chips; and
a plurality of third support structures, each having a first end attached to an upper surface of the one of the first plurality of semiconductor chips and an opposite second end attached to a free end portion of the uppermost semiconductor chip of the plurality of second semiconductor chips.
6 . The semiconductor package of claim 1 , wherein the angle is within a range of 0 degrees to 20 degrees.
7 . The semiconductor package of claim 6 , wherein the stair-step configuration of the plurality of first semiconductor chips extends in a first direction, and wherein each of the first support structures is angled toward the first direction.
8 . The semiconductor package of claim 6 , wherein the stair-step configuration of the plurality of first semiconductor chips extends in a first direction, and wherein each of the first support structures is angled toward a second direction opposite to the first direction.
9 . The semiconductor package of claim 1 , wherein the first support structures comprise at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).
10 . The semiconductor package of claim 1 , wherein a diameter of each of the first support structures is within a range of 1.0 mm to 3.5 mm.
11 . A semiconductor package, comprising:
a package substrate;
a plurality of first semiconductor chips stacked on the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the package substrate, the uppermost semiconductor chip comprising bonding pads on an upper surface thereof, and the uppermost semiconductor chip comprising a free end portion;
conductive wires electrically connecting the bonding pads to the package substrate; and
a plurality of first support structures, each having an elongate linear shape from a first end attached to the upper surface of the package substrate to an opposite second end attached to the free end portion of the uppermost semiconductor chip, wherein the first support structures are inclined at an angle relative to the package substrate.
12 . The semiconductor package of claim 11 , wherein each of the first support structures comprises:
a dummy pad on the package substrate; and
a dummy wire having a first end joined to the dummy pad and an opposite second end contacting a lower surface of the free end portion.
13 . The semiconductor package of claim 11 , further comprising:
at least one second semiconductor chip on the uppermost semiconductor chip of the plurality of first semiconductor chips, the at least one second semiconductor chip comprising a free end portion; and
a plurality of second support structures, each having a first end attached to an upper surface of one of the plurality of first semiconductor chips and an opposite second end attached to the free end portion of the at least one second semiconductor chip.
14 . The semiconductor package of claim 13 , wherein the at least one second semiconductor chip comprises a plurality of second semiconductor chips stacked on the first semiconductor chips in a stair-step configuration opposite to the stair-step configuration of the first semiconductor chips, the plurality of second semiconductor chips having an uppermost semiconductor chip at a second height from an upper surface of one of the first semiconductor chips; and
a plurality of third support structures, each having a first end attached to an upper surface of the one of the first plurality of semiconductor chips and an opposite second end attached to a free end portion of the uppermost semiconductor chip of the plurality of second semiconductor chips.
15 . The semiconductor package of claim 11 , wherein the first support structures comprise at least one of copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).
16 . The semiconductor package of claim 11 , wherein a diameter of each of the first support structures is within a range of 1.0 mm to 3.5 mm.