Hybrid CMOS with fin and nanosheet architectures
A hybrid semiconductor structure, a system, and a method of forming a hybrid semiconductor structure. The hybrid semiconductor structure may include a PFET region, where the PFET region includes a first channel in a fin shape; an NFET region, where the NFET region includes a second channel, the second channel including a nanosheet; and an isolation bar separating the PFET region from the NFET region. The system may include a hybrid semiconductor structure including a PFET region; an NFET region; an isolation bar separating the PFET and NFET region; and a gate surrounding a plurality of sidewalls of the first channel and the second channel. The method may include forming an isolation bar between a first channel material in an NFET region and a second channel material in a PFET region; forming the second channel material into a fin shape; and forming the first channel material into stacked nanosheets.
1 . A hybrid semiconductor structure, wherein the hybrid semiconductor structure comprises:
a PFET region, wherein the PFET region comprises a first channel in a vertically oriented fin shape;
an NFET region, wherein the NFET region comprises a second channel, the second channel comprising a horizontally oriented nanosheet;
a shallow trench isolation (STI) region disposed below and between the PFET region and the NFET region; and
an isolation bar separating the PFET region from the NFET region and extending at least one of the first channel and the second channel and extending below the STI region.
2 . The hybrid semiconductor structure of claim 1 , wherein the isolation bar is connected to the second channel.
3 . The hybrid semiconductor structure of claim 2 , wherein the isolation bar is further connected to a substrate, wherein the substrate is below the PFET region and the NFET region.
4 . The hybrid semiconductor structure of claim 1 , wherein the PFET region may be between 20 nanometers and 40 nanometers from the NFET region.
5 . The hybrid semiconductor structure of claim 1 , further comprising:
a shallow trench isolation (STI) region below and between the PFET region and the NFET region.
6 . The hybrid semiconductor structure of claim 1 , wherein the isolation bar comprises at least one of SIN, SiOCN, SiBCN, SiOC, and SiC.
7 . The hybrid semiconductor structure of claim 1 , where the PFET region further comprises a third channel.
8 . A system, wherein the system comprises:
a hybrid semiconductor structure, the hybrid semiconductor structure comprising:
a PFET region, wherein the PFET region comprises a first channel in a fin shape;
an NFET region, wherein the NFET region comprises a second channel, the second channel comprising a nanosheet;
an isolation bar separating the PFET region from the NFET region and extending above and below both the first channel and the second channel, the isolation bar directly connected to a sidewall of the nanosheet; and
a gate surrounding a plurality of sidewalls of the first channel and the second channel.
9 . The system of claim 8 , wherein the isolation bar is connected to the second channel.
10 . The system of claim 8 , wherein the PFET region may be between 20 nanometers and 40 nanometers from the NFET region.
11 . The system of claim 8 , wherein the hybrid semiconductor structure further comprises a substrate, wherein the substrate is below the PFET region and the NFET region.
12 . The system of claim 11 , wherein the isolation bar is connected to the substrate.
13 . The system of claim 12 , wherein the isolation bar extends above the first channel and the second channel.
14 . The system of claim 8 , wherein the isolation bar comprises at least one of SiN, SiOCN, SiBCN, SiOC, and SiC.
15 . A hybrid semiconductor structure comprising:
a first region;
a second region;
a shallow trench isolation (STI) region below and between the first region and the second region;
a first transistor within the first region and comprising a vertically orientated fin channel;
a second transistor within the second region and comprising a horizontally orientated nanosheet channel; and
an isolation bar separating the vertically orientated fin channel and the horizontally orientated nanosheet channel and extending above at least one of the vertically orientated fin channel and horizontally orientated nanosheet channel and extending below the STI region.
16 . The hybrid semiconductor structure of claim 15 , wherein a sidewall of the horizontally orientated nanosheet channel is directly connected to the isolation bar.
17 . The hybrid semiconductor structure of claim 16 , wherein the isolation bar is further directly connected to a substrate, wherein the substrate is below the first transistor and below the second transistor.
18 . The hybrid semiconductor structure of claim 15 , wherein a top surface of the isolation bar is above respective top surfaces of the vertically orientated fin channel and the horizontally orientated nanosheet channel.
19 . The hybrid semiconductor structure of claim 15 , wherein a top surface of the vertically orientated fin channel and a top surface of the horizontally orientated nanosheet channel are substantially coplanar.
20 . The hybrid semiconductor structure of claim 17 , further comprising:
a first bottom dielectric isolation (BDI) region upon the substrate aligned with the vertically orientated fin channel; and
a second bottom BDI region upon the substrate aligned with the horizontally orientated nanosheet channel.