Test structure and method for forming the same, and semiconductor memory
A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.
1 . A test structure, comprising
a plurality of word lines and a plurality of bit lines, wherein a vertical gate-all-around (VGAA) transistor is formed at an intersection of each word line and each bit line;
the test structure comprises a first area and a second area, wherein the second area is arranged outside the first area, word lines in the first area and word lines in the second area are disconnected, and bit lines in the first area and bit lines in the second area are disconnected; and
a plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested;
a gate contact node and a source contact node; wherein
the gate contact node is located in the first area, and the gate contact node is connected with a control end of the device to be tested through a word line; and
the source contact node is located in the first area, and the source contact node is connected with a first end of the device to be tested through a bit line;
a first metal layer, a second metal layer, and a third metal layer; wherein
the first metal layer covers and is connected with the gate contact node, and the first metal layer extends to an outside of the second area;
the second metal layer covers and is connected with the source contact node, and the second metal layer extends to the another outside of the second area;
the third metal layer covers and is connected with a second end of the device to be tested, and the third metal layer extends to the outside of the second area;
wherein extension directions of the first metal layer, the second metal layer, and the third metal layer to the second area are different, and the first metal layer, the second metal layer and the third metal layer do not intersect with each other.
2 . The test structure of claim 1 , wherein
the first metal layer is configured to connect a gate of the device to be tested, the second metal layer is configured to connect a source of the device to be tested, and the third metal layer is configured to connect a drain of the device to be tested.
3 . The test structure of claim 1 , wherein
a width of the first metal layer in a bit line direction covers three word lines, and the first metal layer does not cover the test array; and
a width of the second metal layer in a word line direction covers three bit lines, and the second metal layer does not cover the test array.
4 . The test structure of claim 1 , wherein
a size of the test array is an (m×n) array, where m and n are both positive integers, and m and n are equal or unequal;
wherein values of m and n include at least any one of the following: 3, 4, 5, 9, or 16.
5 . A semiconductor memory, comprising
the test structure of claim 1 .