Vias with vertically non-uniform or discontinuous stack
Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.
1 . A via structure, comprising:
a substrate;
an opening through the substrate, wherein the opening has a first portion and a second portion under the first portion;
a lining on sidewalls of the first portion of the opening; and
a via filling the opening, wherein the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width,
wherein the via has an uppermost surface at a same level as an uppermost surface of the lining, wherein the second region has a non-uniform thickness through a length of the second region of the via, and wherein an end of the second region of the via opposite from the first region of the via is rounded.
2 . The via structure of claim 1 , wherein the first width is approximately ninety percent of the second width or smaller.
3 . The via structure of claim 1 , wherein the first region of the via is in the first portion of the opening, and wherein the second region of the via is in the second portion of the opening.
4 . The via structure of claim 1 , further comprising:
a step at the junction between the first region of the via and the second region of the via.
5 . The via structure of claim 4 , wherein the step is rounded.
6 . The via structure of claim 1 , wherein a junction between the first region of the via and the second region of the via is tapered.
7 . The via structure of claim 1 , wherein the lining comprises oxygen or nitrogen.
8 . The via structure of claim 1 , wherein the via comprises tungsten.
9 . The via structure of claim 1 , wherein the first region of the via has a non-uniform thickness through a length of the first region of the via.
10 . The via structure of claim 1 , wherein the substrate comprises silicon.
11 . A method of forming a backside via, comprising:
forming an opening in a substrate, wherein the opening has a first portion and a second portion below the first portion;
filling the second portion of the opening with a sacrificial material;
forming a lining along sidewalls of the opening in the first portion of the opening above the sacrificial material;
removing the sacrificial material; and
forming a via in the opening, wherein the via has a first width at the first portion of the opening adjacent to the lining and a second width at the second portion of the opening below the lining, and wherein the via has an uppermost surface at a same level as an uppermost surface of the lining.
12 . The method of claim 11 , wherein a stepped structure is provided at the junction between the first width and the second width.
13 . The method of claim 12 , wherein the stepped structure is rounded.
14 . The method of claim 11 , wherein a junction between the first width and the second width is tapered.
15 . The method of claim 11 , wherein the first width is approximately ninety percent of the second width or smaller.
16 . The method of claim 11 , wherein the lining comprises oxygen or nitrogen.
17 . The method of claim 11 , wherein the via comprises tungsten.
18 . The method of claim 11 , wherein filling the second portion of the opening with a sacrificial material comprises:
filling the first portion of the opening and the second portion of the opening with the sacrificial material; and
recessing the sacrificial material to clear the first portion of the opening.
19 . A semiconductor device, comprising:
a substrate;
a non-planar transistor device with a source and a drain over the substrate;
a via through the substrate and coupled to one of the source and the drain, wherein the via comprises:
a first region with a first width, wherein the first region contacts the one of the source and the drain; and
a second region with a second width below the first region, wherein the second width is greater than the first width, wherein the second region has a non-uniform thickness through a length of the second region of the via, and wherein an end of the second region of the via opposite from the first region of the via is rounded; and
a lining on sidewalls of the first region of the via, wherein the via has an uppermost surface at a same level as an uppermost surface of the lining.
20 . The semiconductor device of claim 19 , wherein a junction between the first region and the second region is a stepped interface.
21 . The semiconductor device of claim 19 , further comprising:
a lining adjacent to the first region of the via.
22 . An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises:
a substrate;
a non-planar transistor device with a source and a drain over the substrate;
a via through the substrate and coupled to one of the source and the drain, wherein the via comprises:
a first region with a first width, wherein the first region contacts the one of the source and the drain; and
a second region with a second width below the first region, wherein the second width is greater than the first width, wherein the second region has a non-uniform thickness through a length of the second region of the via, and wherein an end of the second region of the via opposite from the first region of the via is rounded; and
a lining on sidewalls of the first region of the via, wherein the via has an uppermost surface at a same level as an uppermost surface of the lining.
23 . The electronic system of claim 22 , wherein a junction between the first region and the second region is a stepped interface.